A circuit for processing an input-signal voltage comprises an input capacitance coupled between an input node of the circuit and a sense node of a comparator and a reference capacitance coupled to the sense node of the comparator. A method for processing an input-signal voltage comprises configuring a reference capacitance coupled to an input capacitance; during a charge phase, charging the reference capacitance to a first-level reference voltage; and, during an operative phase, setting the input capacitance to an input-signal voltage to obtain, at the sense node, a sense voltage.

In accordance with an embodiment, a method of operating a switched capacitor circuit includes pre-charging a capacitor using a voltage buffer having an input coupled to an input node of the switched capacitor circuit and an output coupled to the capacitor, coupling the input node to the capacitor, wherein a first charge is collected on the capacitor, and integrating the first charge using an integrator.

Self-interference cancellers are provided. The self-interference cancellers can include multiple second-order, N-path G.sub.m-C filters. Each filter can be configured to cancel self-interference on a channel of a desired bandwidth. Each filter can be independently controlled using a variable transmitter resistance, a variable receiver resistance, a variable baseband capacitance, a variable transconductance, and a variable time shift between local oscillators that control switches in the filter. By controlling these variables, magnitude, phase, slope of magnitude, and slope of phase of the cancellers frequency responses can be controlled for self-interference cancellation. A calibration process is also provided for configuring the canceller.

There is provided a variable RF filter receiving an input differential radio frequency signal from a differential input terminals (501, 502) and allowing a radio frequency signal around a desired frequency to pass therethrough, wherein first passive mixers (901, . . . , 904) driven by a rectangular wave clock signal having an arbitrarily determined frequency are connected in parallel to a signal line across the differential input terminals (501, 502) and differential output terminals (918, 919), and wherein a load of each of the first passive mixers (901, . . . , 904) is configured by inductors (903, . . . , 906). Further, as a clock signal driving each of the first passive mixers (901, . . . , 904), an odd-multiple-wave Lo signal (for example, a triple-wave Lo signal) is used, the signal having a frequency odd-multiple times (for example, three times) as high as that of the Lo signal which is the fundamental wave of the passing radio frequency signal.

Certain aspects of the present disclosure provide N-path filters with wider passbands and steeper rejection than conventional N-path filters with only a single pole in each filter path. These N-path filters also have a flatter passband with decreased passband droop. One example N-path filter generally includes a plurality of branches selectively connected with a common node, each branch of the N-path filter comprising a switch connected in series with an impedance comprising a common drain amplifier circuit. In certain aspects, the amplifier circuit may include a degeneration circuit for stability and/or a poly-phase feedback circuit to reduce in-band peaking.

Devices and methods that aim to improve flicker noise rejection in switched-capacitor (SC) integrators are disclosed. An example SC integrator includes a first and a second sampling capacitors, an amplifier, an integrating capacitor, coupled at least to an output of the amplifier, and a switching arrangement. By adding (i.e., integrating in the integrating capacitor) sign-inverted samples of a flicker noise of the amplifier at every clock cycle of a master clock and by keeping the time distance/delay between those samples relatively small regardless of the master clock frequency, such a SC integrator may provide improvements in terms of rejecting the flicker noise of the amplifier.

An aspect includes a filtering method including operating a first filter to filter a first input signal to generate a first output signal; operating a second filter to filter a second input signal to generate a second output signal; and merging at least a portion of the second filter with the first filter to filter a third input signal to generate a third output signal. Another aspect includes a filtering method including operating switching devices to configure a filter with a first set of pole(s); filtering a first input signal to generate a first output signal with the filter configured with the first set of pole(s); operating the switching devices to configure the filter with a second set of poles; and filtering a second input signal to generate a second output signal with the filter configured with the second set of poles.

This disclosure describes systems, methods, and apparatus for a digital-to-analog (DAC) converter, that can be part of a variable capacitor and/or a match network. The DAC can include a digital input, an analog output, N contributors (e.g., switched capacitors), and an interconnect topology connecting the N contributors, generating a sum of their contributions (e.g., sum of capacitances), and providing the sum to the analog output. The N contributors can form a sub-binary sequence when their contributions to the sum are ordered by average contribution. Also, the gap size between a maximum contribution of one contributor, and a minimum contribution of a subsequent contributor, is less than D, where D is less than or equal to two time a maximum contribution of the first or smallest of the N contributors.

A novel and useful discrete time IIR bandpass filter is disclosed that takes advantage of clock phase reuse thereby leading to significant improvements in filtering, especially stop band rejection in comparison to prior art filters. The bandpass filter of the present invention achieves improved filtering performance without adding any additional clock phases to the circuit. In particular, reuse of the already existing clock phases increases the order and performance of the filter. The invention exploits reuse of the clock phases to provide higher order filtering along with a discrete time IIR filter design which is capable of operating at high frequency. Consequently, much better filtering is achieved and the quality factor of the filter is improved leading to sharper transition bands especially for close-in band blockers in modern 4G/5G receivers.

A switched capacitor circuit includes an output capacitor, a first transmission switch, a first reference buffer, a second transmission switch, a second reference buffer and a charge compensation circuit. The output capacitor includes a first terminal and a second terminal, wherein the first terminal is coupled to an output terminal of the switched capacitor circuit, and the second terminal is coupled to a reference node. The first transmission switch is coupled to the reference node. The first reference buffer is coupled to the first transmission switch. The second transmission switch is coupled to the reference node. The second reference buffer is coupled to the second transmission switch. The charge compensation circuit is coupled to the reference node.