The present disclosure provides a power integrated circuit (IC) for a switching power supply device that generates an output voltage based on an input voltage. The circuit includes: a high-side transistor, disposed between an input terminal applied with the input voltage and a switch terminal; and a low-side transistor, disposed between the switch terminal and a ground terminal. A feedback control for turning on or off the transistor is performed based on a feedback voltage corresponding to the output voltage. A protection circuit is capable of performing a protection operation for turning on the high-side transistor or the low-side transistor regardless of the feedback control based on a switch voltage at the switch terminal and the input voltage, based on a backflow current from the ground terminal to the switch terminal, or based on the input voltage and a predetermined determination voltage.

A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.

A gate driver circuit includes first through third transistors, a first voltage clamp, and control logic. The first transistor has a first control input and first and second current terminals. The first current terminal couples to a first voltage terminal. The first voltage clamp couples between the first voltage terminal and the first control input. The second transistor couples between the first control input and the second voltage terminal. The third transistor couples between the first control input and the second voltage terminal. The third transistor is smaller than the second transistor. The control logic is configured to turn on both the second and third transistors to thereby turn on the first transistor, and the first control logic configured to turn off the second transistor after the first transistor turns on while maintaining in an on-state the third transistor to maintain the first transistor in the on-state.

Embodiments of the present invention provide for a core stage in an application-specific integrated circuit core which drives both a clock pulse signal and a clock pulse negative/complement signal concurrently, thereby resulting in perfectly aligned signals. The core stage can include a pulse generator, a clock distribution circuit, and a set of latches.

A level-shifting output buffer has cascode transistors with varying rather than fixed gate bias voltages. An adaptive regulator bypasses the I/O pad voltage to a regulator output when the I/O begins switching, but later clamps the regulator output to a middle bias voltage. The regulator output can be applied to a supply terminal of a buffer that drives the gate of the cascode transistor. Since the adaptive regulator follows the I/O pad voltage as switching begins, a voltage boost is provided to the gates of the cascode transistors, allowing for higher currents or smaller cascode transistors and preventing over-voltage stress. The adaptive regulator has an n-channel bypass transistor between the I/O pad and the regulator output, and an n-channel clamp transistor between the regulator output and the middle bias, with a gate driven from the I/O pad by either a p-channel gate-biasing transistor or an n-channel gate-biasing transistor.

A high-power pulse generator (1), belonging to the LTD family, includes two series of power modules, one series of standard modules (3s) and one series of modified modules (3m), each including a switch (6s; 6m), provided with a trigger electrode (9s; 9m), positioned in series between two capacitors (4s; 4m), the modified modules being designed to produce a pulse at a frequency substantially three times the frequency of the standard modules, and a trigger device (13) designed to control the standard and modified switches (6s; 6m) via a single trigger signal applied to the trigger electrode (9s; 9m) of same. The trigger signal is applied to the switches through a trigger impedance (10m; 10s) that is different between the standard and modified modules, and the plateau slope of the generated pulse depends on the difference between the value of the standard impedance and that of the modified impedance.

An example output driver includes a plurality of output circuits coupled in parallel between a first voltage supply node and a second voltage supply node. Each of the plurality of output circuits includes a differential input that is coupled to receive a logic signal of a plurality of logic signals and a differential output that is coupled to a common output node. The output driver further includes voltage regulator(s), coupled to the voltage supply node(s), and a current compensation circuit. The current compensation circuit includes a switch coupled in series with a current source, where the switch and the current source are coupled between the first voltage supply node and the second voltage supply node. An event detector is coupled to the switch to supply an enable signal and to control state of the enable signal based on presence of a pattern in the plurality of logic signals.

A clock signal generation circuit, a method for generating a clock signal, and an electronic device are provided, relating to the field of communications technology. In the clock signal generation circuit, an initial clock providing circuit can generate an initial clock signal having an initial frequency; a control word providing circuit can determine a target frequency offset of the initial frequency based on a detected target parameter and generate a frequency control word based on the target frequency offset; a target clock generating circuit can generate a target clock signal having a target output frequency based on the frequency control word and the initial clock signal, wherein the target output frequency is negatively correlated with a value of the frequency control word and positively correlated with the initial frequency.

System and method for driving a bipolar junction transistor for a power converter. The system includes a current generator configured to output a drive current signal to a bipolar junction transistor to adjust a primary current flowing through a primary winding of a power converter. The current generator is further configured to output the drive current signal to turn on the bipolar junction transistor during a first time period, a second time period, and a third time period, the second time period separating the first time period from the third time period, drive the bipolar junction transistor to operate in a hard-saturation region during the first time period and the second time period, and drive the bipolar junction transistor to operate in a quasi-saturation region during the third time period.

It is an object of the present invention to provide a buffer circuit that reduces a reverse voltage applied to transistors being a complementary pair during turn-on and turn-off. A buffer circuit is a buffer circuit that turns on and turns off a switching element and includes a drive-side element that has an end connected to a base of a drive transistor and a sink-side element that has an end connected to a base of a sink transistor. The drive-side element and the sink-side element are respectively a drive-side diode and a sink-side diode, or a drive-side capacitor and a sink-side capacitor.