A RXLOS deglitch apparatus for a receiver is provided. The RXLOS deglitch apparatus includes a sampler, an edge detecting unit and a finite state machine. The sampler receives a recovered clock, and samples a RXLOS signal according to the recovered clock. Consequently, a sampled RXLOS signal is generated. The edge detecting unit receives the RXLOS signal. When a logic level of the RXLOS signal is changed, an edge detection signal is activated by the edge detecting unit. The finite state machine receives the edge detection signal and the sampled RXLOS signal, generates an edge rest signal to control the edge detecting unit, and outputs a filtered RXLOS signal.

A RXLOS deglitch apparatus for a receiver is provided. The RXLOS deglitch apparatus includes a sampler, an edge detecting unit and a finite state machine. The sampler receives a recovered clock, and samples a RXLOS signal according to the recovered clock. Consequently, a sampled RXLOS signal is generated. The edge detecting unit receives the RXLOS signal. When a logic level of the RXLOS signal is changed, an edge detection signal is activated by the edge detecting unit. The finite state machine receives the edge detection signal and the sampled RXLOS signal, generates an edge rest signal to control the edge detecting unit, and outputs a filtered RXLOS signal.

An apparatus, comprising a clock adapted to provide a clock signal alternating with a cycle between a first level and a second level if a timing violation is not detected; a first latch adapted to be clocked such that it passes a first signal when the clock signal is at the first level; a second combinational logic adapted to output a second signal based on the first signal passed through the first latch; a second latch adapted to be clocked such that it passes the second signal when the clock signal is at the second level; a detecting means adapted to detect the timing violation of at least one of the first signal and of the second signal; a time stretching means adapted to stretch, if the timing violation is detected, the clock such that the clock alternates between the first level and the second level with a delay.

An electronic circuit includes an input configured to receive an input signal and an output configured to be coupled to load, an output transistor including a load path and a control node, the load path being connected between the output and a first supply node, a drive transistor including a load path and a control node, the load path being connected to the control node of the output transistor, a first electronic switch connected in series with the load path of the drive transistor, a biasing circuit including an internal impedance and connected between the control node of the drive transistor and the first supply node, and a control circuit configured to receive the input signal and to drive the first electronic switch based on the input signal.

The present disclosure provides circuits and methods for generating clock-signals. An exemplary clock-signal generation circuit includes a delay buffer unit; an inverter unit coupled to the delay buffer unit; a first delay unit having a first NAND Boolean calculation sub unit, a first sub delay unit and a first level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a first delayed clock-signal; and a second delay unit having a second NAND Boolean calculation sub unit, a second sub delay unit and a second level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a second delayed clock signal.

The present disclosure presents a circuit, a method, and a system to drive a half-bridge switch using depletion (D) mode compound semiconductor (III-V) switching transistors for a DC-DC converter using at least one driver to drive the switches of the circuit. Also included is at least one charge pump electrically connected to a gate of the transistor, to maintain a voltage that holds the transistor in an off-state. The circuit includes AC coupling capacitors to level shift a voltage and realize fast transistor switching.

In accordance with one or more aspects of the disclosed embodiments, a drive circuit having a source of modulation for producing a modulated signal, a level shifter configured to receive the modulated signal and produce a level-shifted driver signal, an inverter circuit configured to receive the level-shifted driver signal and produce a MOSFET control signal, and at least one p-channel metal oxide semiconductor field effect transistor (MOSFET) configured to receive the MOSFET control signal and modulate an application of high current to a load, where the MOSFET control signal is supplied directly to the p-channel MOSFET through the inverter circuit.

According to an embodiment, a module M1 includes an internal circuit 14, and a standard information transmitting unit 15 that transmits a result of a comparison between a voltage supplied from an externally-disposed control device 1 and a threshold voltage specified based on a communication standard of the internal circuit 14 to the control device 1 as information on the communication standard of the internal circuit 14. As a result, the module M1 can communicate with the control device 1 according to a correct communication standard.

Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same V.sub.DS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same V.sub.GS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both V.sub.GS and V.sub.DS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.

A circuit may include an output circuit with an output circuit output impedance and a control circuit. The output circuit may include a driver circuit that includes an output terminal and a driver circuit output impedance at the output terminal. The output circuit may also include an adjustable impedance circuit that includes an adjustable impedance. The adjustable impedance circuit may be coupled between the output terminal of the driver circuit and a signal transmission line. The output circuit output impedance may be based on the driver circuit output impedance and the adjustable impedance. The control circuit may be coupled to the adjustable impedance circuit. The control circuit may be configured to adjust the adjustable impedance of the adjustable impedance circuit such that the output circuit output impedance approximately equals a particular impedance.