A method for controlling an electrical switch using a driver waveform, wherein the driver waveform comprises: a first time period, T.sub.1, associated with a first current, I.sub.G_high; a second time period, T.sub.2, associated with a second current, I.sub.G_low; wherein: the first current of the driver waveform, I.sub.G_high, is larger than the second current of the driver waveform, I.sub.G_low; and the first time period, T.sub.1, has a first duration and the second time period, T.sub.2, has a second duration. The method comprising: determining an optimised first duration by repeatedly modifying the first duration until an overshoot in an output waveform generated by switching the electrical switch using the driver waveform is less than a threshold; determining an optimised second duration based on the optimised first duration; and switching the electrical switch using the optimised first duration and the optimised second duration.

A method includes in a first operating mode of a load switch comprising two back-to-back connected transistors, reducing at least one of a first gate-to-source voltage and a second gate-to-source voltage of the two back-to-back connected transistors from a normal gate drive voltage potential to a reduced gate drive voltage potential, and in a second operating mode of the load switch, increasing the at least one of the first gate-to-source voltage and the second gate-to-source voltage of the two back-to-back connected transistors from the reduced gate drive voltage potential to the normal gate drive voltage potential.

An integrated circuit (IC) includes: an input terminal; an output terminal; a first reference voltage terminal and a second reference voltage terminal; a high-side power switch coupled between the first reference voltage terminal and the output terminal; a low-side power switch coupled between the output terminal and the second reference voltage terminal; a first combinational logic and a second combination logic that are coupled to the input terminal; a first driver coupled between the first combinational logic and the high-side power switch; a second driver coupled between the second combinational logic and the low-side power switch; and first comparators coupled to the second combinational logic, where the first comparators are configured to compare a voltage difference between load path terminals of the high-side power switch with a first threshold and a second threshold.

A power-on reset circuit 10 has: an enhancement-type PMOS transistor P1 whose source is connected to VDD and whose drain is connected to node VJG; a depletion-type NMOS transistor D1 whose drain is connected to the node VJG; a first resistor portion having resistors R1, R2 that are connected in series, and whose one end is connected to a source of the depletion-type NMOS transistor D1, and whose another end is connected to GND, and at which a region between the resistors R1, R2 is connected to a gate of the enhancement-type PMOS transistor P1; and an inverter whose input is connected to the node VJG, and that outputs a reset signal.

Some embodiments may include a nanosecond pulser comprising a plurality of solid state switches; a transformer having a stray inductance, L.sub.s, a stray capacitance, C.sub.s, and a turn ratio n; and a resistor with a resistance, R, in series between the transformer and the switches. In some embodiments, the resonant circuit produces a Q factor according to $Q=\frac{1}{R}\sqrt{\frac{L_s}{C_s}};$
and the nanosecond pulser produces an output voltage V.sub.out from an input voltage V.sub.in, according to V.sub.out=QnV.sub.in.

A system for controlling supply of a device. The device can be a power retention device that requires to be permanently powered. To this end, it can be alternatively powered by a power supply, in a first mode, or by a battery, in a second mode. At least one sensor of the system acquires data related to the battery, such as environmental data, the voltage of the battery or the discharge current of the battery. Based on the data and at least one characteristic curve of the battery, a battery monitoring module is configured to switch between the first and second modes to improve the lifetime of the battery.

A selection circuit architecture makes it possible to perform upward and/or downward transitions in sets of sequences of slow and fast phases so as at the same time to solve the problems of inductive switching noise and the problems of currents in the supply rails. This solution has multiple advantages linked to the ease of implementation and flexibility of configurations that are possible for adapting to the specific constraints when designing the circuit.

A semiconductor device that can perform product-sum operation with low power is provided. The semiconductor device includes a switching circuit. The switching circuit includes first to fourth terminals. The switching circuit has a function of selecting one of the third terminal and the fourth terminal as electrical connection destination of the first terminal, and selecting the other of the third terminal and the fourth terminal as electrical connection destination of the second terminal, on the basis of first data. The switching circuit includes a first transistor and a second transistor each having a back gate. The switching circuit has a function of determining a signal-transmission speed between the first terminal and one of the third terminal and the fourth terminal and a signal-transmission speed between the second terminal and the other of the third terminal and the fourth terminal on the basis of potentials of the back gates. The potentials are determined by second data. When signals are input to the first terminal and the second terminal, a time lag between the signals output from the third terminal and the fourth terminal is determined by the first data and the second data.

A device for hooking up a signal-outputting mechanism with two potential sensors each of which has allocated to it two evaluation terminals, wherein the potentials of the evaluation terminals depend inversely on the resistances between the respective evaluation terminals.

A method for active gate driving a switching circuit, wherein: a characteristic of a waveform controlled by the switching circuit is represented by a function mapping an input variable to an output metric, and wherein: the input variable comprises: a design variable having a first set of possible values; and an environmental variable having a second set of possible values, wherein the environmental variable is observable but not controllable. The method comprising: performing Bayesian optimisation on the function to generate a model of the function, wherein a next value of the design variable for evaluating the function is selected based on values of an acquisition function associated with a predicted value of the environmental variable; determining a first value of the design variable that optimises the model of the function; and controlling the switching circuit according to the first value of the design variable.