A power supply unit for use with thermostats or other like devices requiring power. A power supply unit may be designed to keep electromagnetic interference emissions at a minimum, particularly at a level that does not violate governmental regulations. A unit may be designed so that there is enough power for a triggering a switch at about a cross over point of a waveform of input power to the unit. Power for triggering may come from a storage source rather than line power to reduce emissions on the power line. Power for the storage source may be provided with power stealing. Power stealing may require switching transistors which can generate emissions. Gate signals to the transistors may be especially shaped to keep emissions from transistor switching at a minimum.

A power supply unit for use with thermostats or other like devices requiring power. A power supply unit may be designed to keep electromagnetic interference emissions at a minimum, particularly at a level that does not violate governmental regulations. A unit may be designed so that there is enough power for a triggering a switch at about a cross over point of a waveform of input power to the unit. Power for triggering may come from a storage source rather than line power to reduce emissions on the power line. Power for the storage source may be provided with power stealing. Power stealing may require switching transistors which can generate emissions. Gate signals to the transistors may be especially shaped to keep emissions from transistor switching at a minimum.

A power switching circuit includes a first switch circuit, a second switch circuit, a control circuit, and a driver circuit. The first switch circuit receives a first power voltage and coupled to an output terminal. The first switch circuit includes a first P-type transistor and a second P-type transistor coupled in series. The second switch circuit receives a second power voltage and coupled to the output terminal. The second switch circuit includes a third P-type transistor and a fourth P-type transistor coupled in series. The control circuit generates a control signal according to an output voltage at the output terminal, a power state signal, and one of the first power voltage and the second power voltage. The driver circuit generates a first driving signal or a second driving signal according to the control signal to control the first switch circuit or the second switch circuit.

A device that includes a printed circuit board (PCB), a metal conductor, and a transistor. The metal conductor includes first and second oppositely facing surfaces. The transistor includes first and second terminals between which current is transmitted when the transistor is activated, and a gate terminal for controlling the transistor. The first terminal is sintered to the first surface, and the gate is electrically connected to a trace on the PCB.

A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to check proper operation of the die-to-die interconnect, and a receive circuit coupled to the die-to-die interconnect, the receive circuit including at least one flip flop to function as part of a multiple input shift register (MISR).

A semiconductor integrated circuit includes: a p.sup.−-type semiconductor substrate defining a high-potential side circuit area and a low-potential side circuit area separated from each other; a high-side n well provided in an upper part of the semiconductor substrate in the high-potential side circuit area; a high-side p well provided in the high-side n well; and a p-type semiconductor region provided in an upper part of the semiconductor substrate in the low-potential side circuit area; and n.sup.+-type semiconductor region provided to be brought contact with the p-type semiconductor region, wherein a whole n-type semiconductor region including the n.sup.+-type semiconductor region, has an impurity concentration higher than an impurity concentration of the high-side n well.

A semiconductor integrated circuit includes: a p.sup.−-type semiconductor substrate defining a high-potential side circuit area and a low-potential side circuit area separated from each other; a high-side n well provided in an upper part of the semiconductor substrate in the high-potential side circuit area; a high-side p well provided in the high-side n well; and a p-type semiconductor region provided in an upper part of the semiconductor substrate in the low-potential side circuit area; and n.sup.+-type semiconductor region provided to be brought contact with the p-type semiconductor region, wherein a whole n-type semiconductor region including the n.sup.+-type semiconductor region, has an impurity concentration higher than an impurity concentration of the high-side n well.

An electronic circuit includes a first oscillator, a second oscillator and ancillary circuitry. The first oscillator is configured to generate a first clock signal and has a first wake-up delay. The second oscillator is configured to generate a second clock signal and has a second wake-up delay that is shorter than the first wake-up delay. The ancillary circuitry is configured to provide the second clock signal as an output clock signal during wake-up of the first oscillator, and, following the first wake-up delay, to provide the first clock signal as the output clock signal.

A resistor calibration system includes a reference resistor, a first control circuit, a second control circuit, a comparator, a multiplexer and a de-multiplexer. The first control circuit calibrates a first resistor and a duplicated first resistor. The second control circuit calibrates a second resistor. The comparator includes a first input terminal receiving a reference voltage, a second input terminal and an output terminal. The multiplexer includes a first input terminal coupled to the reference resistor and the first resistor, a second input terminal coupled to the duplicated first resistor and the second resistor, and an output terminal coupled to the second input terminal of the comparator. The de-multiplexer includes an input terminal coupled to the output terminal of the comparator, a first output terminal coupled to the first control circuit, and a second output terminal coupled to the second control circuit.

In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack.