A circuit for compensating quantized noise in fractional-N frequency synthesizer, comprising a PLL circuit that locks a phase compensated signal to a phase of a reference phase, wherein the phase lock loop circuit comprises a frequency divider and a phase frequency detector; a sigma-delta modulation and phase difference calculator coupled to the frequency divider generating an accumulated phase error by accumulating all previous differences between an input of the frequency divider and an output of the frequency divider within a period; a digital controlled delay line coupled to both the frequency divider and the SDM and Phase Difference calculator and generates the phase compensated signal by multiplying the accumulated phase error with a delay control word; and the phase frequency detector further generates a phase error by comparing the phase compensated signal with the reference clock.

A circuit for compensating quantized noise in fractional-N frequency synthesizer, comprising a PLL circuit that locks a phase compensated signal to a phase of a reference phase, wherein the phase lock loop circuit comprises a frequency divider and a phase frequency detector; a sigma-delta modulation and phase difference calculator coupled to the frequency divider generating an accumulated phase error by accumulating all previous differences between an input of the frequency divider and an output of the frequency divider within a period; a digital controlled delay line coupled to both the frequency divider and the SDM and Phase Difference calculator and generates the phase compensated signal by multiplying the accumulated phase error with a delay control word; and the phase frequency detector further generates a phase error by comparing the phase compensated signal with the reference clock.

A pleat counter and methods are provided to accurately count the number of pleats in a corrugated sheet of material to be used for the production of air filters. The pleat counter comprises a pleat detector mounted underneath a mounting board for counting the pleats. The mounting board is configured to position the pleat detector adjacent to the corrugated sheet of filter material. The pleat detector includes one or more sensors configured to detect the presence of individual pleats comprising the corrugated sheet. The pleat counter includes an interface configured to enable coupling the pleat counter with a data processing system. The data processing system may comprise any of a desktop, a tablet, a server, a mobile phone, a media player, a personal digital assistant (PDA), a personal communicator, a network router or hub, a wireless access point (AP) or repeater, a set-top box, or a combination thereof.

A pleat counter and methods are provided to accurately count the number of pleats in a corrugated sheet of material to be used for the production of air filters. The pleat counter comprises a pleat detector mounted underneath a mounting board for counting the pleats. The mounting board is configured to position the pleat detector adjacent to the corrugated sheet of filter material. The pleat detector includes one or more sensors configured to detect the presence of individual pleats comprising the corrugated sheet. The pleat counter includes an interface configured to enable coupling the pleat counter with a data processing system. The data processing system may comprise any of a desktop, a tablet, a server, a mobile phone, a media player, a personal digital assistant (PDA), a personal communicator, a network router or hub, a wireless access point (AP) or repeater, a set-top box, or a combination thereof.

A digital-to-time converter (DTC) circuit. The DTC circuit includes a charge node. A variable current source has a source input and a source output. The source input is coupled to a DTC digital input and the source output is coupled to the charge node. A capacitor has a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is coupled to the charge node. A comparator has a first comparator input, a second comparator input, and a comparator output. The first comparator input is coupled to the charge node, the second comparator input is coupled to a reference voltage terminal, and the comparator output is coupled to a DTC output. A pre-charge circuit has a pre-charge control input and a pre-charge output. The pre-charge control input is coupled to a DTC pre-charge input and the pre-charge output is coupled to the capacitor.

A frequency divider includes a first shifter and a second shifter. The first shifter includes first to M-th clock control components connected together to form a first ring. The control components in the first shifter are controlled by an input clock signal such that signals are shifted along the first ring. An output of selected clock control components in the first shifter is provided as a carry signal of the first shifter. The second shifter includes first to N-th clock control components connected together to form a second ring. The control components in the second shifter are controlled by the carry signal of the first shifter such that the signals are shifted along the second ring. An output of selected clock control components in the second shifter is provided as a carry signal of the second shifter. M and N are integers greater than one.

A frequency divider includes a first shifter and a second shifter. The first shifter includes first to M-th clock control components connected together to form a first ring. The control components in the first shifter are controlled by an input clock signal such that signals are shifted along the first ring. An output of selected clock control components in the first shifter is provided as a carry signal of the first shifter. The second shifter includes first to N-th clock control components connected together to form a second ring. The control components in the second shifter are controlled by the carry signal of the first shifter such that the signals are shifted along the second ring. An output of selected clock control components in the second shifter is provided as a carry signal of the second shifter. M and N are integers greater than one.

A method of sensing a temperature of a semiconductor device, includes: measuring, by a time measuring circuit, time until a count value, which is obtained from a counter by counting a first signal having a frequency corresponding to a first voltage, reaches a largest count value which can be counted by the counter; and obtaining, by the counter, a piece of digital information corresponding to the first voltage based on a count value obtained by counting a second signal having a frequency corresponding to a second voltage, which is different from the first voltage, based on the time measured by the time measuring circuit, the first voltage depending upon the temperature of the semiconductor device.

A method of sensing a temperature of a semiconductor device, includes: measuring, by a time measuring circuit, time until a count value, which is obtained from a counter by counting a first signal having a frequency corresponding to a first voltage, reaches a largest count value which can be counted by the counter; and obtaining, by the counter, a piece of digital information corresponding to the first voltage based on a count value obtained by counting a second signal having a frequency corresponding to a second voltage, which is different from the first voltage, based on the time measured by the time measuring circuit, the first voltage depending upon the temperature of the semiconductor device.

A multi-modulus frequency divider includes a frequency division module, a frequency selection module, and a retiming module. The frequency division module is configured to receive an input signal and perform mufti-mode frequency processing on the input signal, so as to generate and output a plurality of divided signals to the frequency selection module. The frequency selection module is configured to receive the plurality of divided signals from the frequency division module, select a divided signal having a desired frequency from among the plurality of divided signals, and output the selected divided signal to the retiming module. The retiming module is configured to receive the selected divided signal from the frequency selection module, perform a retiming operation on the selected divided signal, and output a retimed selected divided signal.