A multi-modulus frequency divider includes a frequency division module, a frequency selection module, and a retiming module. The frequency division module is configured to receive an input signal and perform mufti-mode frequency processing on the input signal, so as to generate and output a plurality of divided signals to the frequency selection module. The frequency selection module is configured to receive the plurality of divided signals from the frequency division module, select a divided signal having a desired frequency from among the plurality of divided signals, and output the selected divided signal to the retiming module. The retiming module is configured to receive the selected divided signal from the frequency selection module, perform a retiming operation on the selected divided signal, and output a retimed selected divided signal.

Frequency divider techniques are disclosed which can be used to address two problems: when an incorrect division occurs if the modulus control changes before the divide cycle is complete, and when an incorrect division occurs due to a boundary crossing (e.g., power-of-2 boundary crossing in a fractional-N PLL application). In one embodiment, a frequency divider is provided comprising a plurality of flip-flops operatively coupled to carry out division of an input frequency, and configured to generate a modulus output and receive a divided clock signal of a previous cell. An additional flip-flop is selectively clocked off one of the modulus output or the divided clock of the previous stage, depending at least in part on a Skip control signal applied to a data input of the additional flip-flop, and is further configured to selectively reset the plurality of flip-flops to a state that will result in a correct divide ratio.

Frequency divider techniques are disclosed which can be used to address two problems: when an incorrect division occurs if the modulus control changes before the divide cycle is complete, and when an incorrect division occurs due to a boundary crossing (e.g., power-of-2 boundary crossing in a fractional-N PLL application). In one embodiment, a frequency divider is provided comprising a plurality of flip-flops operatively coupled to carry out division of an input frequency, and configured to generate a modulus output and receive a divided clock signal of a previous cell. An additional flip-flop is selectively clocked off one of the modulus output or the divided clock of the previous stage, depending at least in part on a Skip control signal applied to a data input of the additional flip-flop, and is further configured to selectively reset the plurality of flip-flops to a state that will result in a correct divide ratio.

In described examples, an apparatus includes: a counter configured to receive a reference clock signal and having a next state input and a current state output; a multiplexer coupled to the next state input of the counter, configured to output one of an incremented next state value and a corrected next state count value responsive to a count correction select control signal; a seconds reference circuit coupled to the current state output of the counter, configured to output a seconds reference signal; an incrementer coupled to the current state output of the counter, configured to output the incremented next state value; and a calibration compensation circuit coupled to a compensate up down input signal and to the current state output of the counter, configured to output the corrected next state count value and the count correction select control signal.

A timing method and a timing device are disclosed. A Gray code count output may be obtained by performing a Gray code count on a basic clock. Then m number of sub-clocks may be obtained by separately performing a phase shift on a least significant bit output of the Gray code count output, where a phase difference between each of the m number of sub-clocks and the least significant bit output may satisfy: =n and 90, 180 may be divisible by with no remainder, and n may be an integer greater than 0 and less than 180/. If 90 is divisible by with no remainder, m=180/2; and if 90 is divisible by with a remainder, m=180/1. When a predetermined event occurs, a timing result of the predetermined event may be obtained according to the Gray code count output value, outputs of the m number of sub-clocks, a period of the basic clock, and the .

A synchronization signal generation circuit and a synchronization method among a plurality of devices are proposed. The synchronization signal generation circuit includes a clock signal generator and a controller. The clock signal generator generates a reference clock signal. The controller receives an input clock signal from a host end device and generates a plurality of candidate clock signals through a plurality of counting operations based on the reference clock signal. The controller selectively transmits one of the candidate clock signals to each peripheral device according to request information corresponding to each peripheral device. The candidate clock signals and the input clock signal have mutually aligned start time points in each frame period.

A synchronization signal generation circuit and a synchronization method among a plurality of devices are proposed. The synchronization signal generation circuit includes a clock signal generator and a controller. The clock signal generator generates a reference clock signal. The controller receives an input clock signal from a host end device and generates a plurality of candidate clock signals through a plurality of counting operations based on the reference clock signal. The controller selectively transmits one of the candidate clock signals to each peripheral device according to request information corresponding to each peripheral device. The candidate clock signals and the input clock signal have mutually aligned start time points in each frame period.

At least one embodiment of the present disclosure provides a frequency divider, an electronic device and a frequency dividing method. The frequency divider includes a duty cycle correction circuit and a frequency divider circuit. The duty cycle correction circuit is configured to receive a first clock signal, and perform a first processing on the first clock signal to generate a first processed signal. The frequency dividing circuit is configured to receive the first processed signal, and perform a second processing on the first processed signal to generate a second processed signal. The duty cycle correction circuit is further configured to receive the second processed signal, and perform a third processing on the second processed signal to generate a third processed signal. The frequency divider can correct the duty cycle of the output clock signal while dividing the frequency.

A method includes receiving electromagnetic signals containing pulses. The method also includes converting the pulses contained in the electromagnetic signals into an electrical signal that identifies at least some of leading or trailing edges of the pulses. The method further includes repeatedly (i) accumulating the electrical signal to generate a voltage using an integrating circuit and (ii) resetting the integrating circuit in response to the voltage of the integrating circuit meeting or exceeding a threshold voltage. In addition, the method includes providing a count value identifying a number of times that the voltage of the integrating circuit meets or exceeds the threshold voltage. Each time the voltage of the integrating circuit meets or exceeds the threshold voltage is representative of a specific number of pulses received in the electromagnetic signals.

A method includes receiving electromagnetic signals containing pulses. The method also includes converting the pulses contained in the electromagnetic signals into an electrical signal that identifies at least some of leading or trailing edges of the pulses. The method further includes repeatedly (i) accumulating the electrical signal to generate a voltage using an integrating circuit and (ii) resetting the integrating circuit in response to the voltage of the integrating circuit meeting or exceeding a threshold voltage. In addition, the method includes providing a count value identifying a number of times that the voltage of the integrating circuit meets or exceeds the threshold voltage. Each time the voltage of the integrating circuit meets or exceeds the threshold voltage is representative of a specific number of pulses received in the electromagnetic signals.