A system and method for efficiently generating clock signals are described. In various implementations, an integrated circuit includes multiple clock frequency dividers both at its I/O boundaries and across its die. A clock frequency divider utilizes a first clock divider and a second clock divider that receive input clock signals with an initial phase difference between them. The first clock divider and the second clock divider generate output clock signals that have frequencies that are a fraction of the frequencies of the received input clock signals. The second clock divider uses a combined multiplexer and flip-flop (combined mux-flop) circuit. The combined mux-flop circuit receives a reset signal that is asserted asynchronously with respect to an input clock signal received by the second clock divider. The second clock divider generates an output clock signal that has the initial phase difference with an output clock signal of the first clock divider.

A resistive gas sensor is provided. The resistive gas sensor includes a sensing circuit and a determination circuit. The sensing circuit senses a gas to generate a detection signal. The determination circuit performs a frequency-division operation on the detection signal by a frequency-division parameter to generate a frequency-division signal, counts a half of a period of the frequency-division signal to generate a half-period count value, and determines concentration of the gas according to the half-period count value. The determination circuit determines the frequency-division parameter according to the half-period count value.

A pulse density modulation method includes the following steps: S01, obtaining a number of bits n of a binary density value d, setting a number of bits of a counter as n, an initial value of the counter is 0 or 1; S02, searching for a rightmost 1: obtaining a number of bits j of the rightmost 1 of a current value i of the counter counted from right to left; a number in the counter is a binary number; a minimum value of j is 1; S03, determining whether corresponding bits are equal; S04, adding the value i of the counter by 1, proceeding to a next period, and turning to the step S02.

One or more gray code counters, counter arrangements, and phase-locked loop (PLL) circuits are provided. A gray code counter comprises a set of cells, such as standard cells, that output a gray code signal. The gray code counter comprises a pre-ready cell that provides an early signal, generated based upon an early clock, to one or more cells to reduce delay. A counter arrangement comprises one or more counter groups configured to provide pixel count levels for pixels, such as pixels of an image sensor array. A counter group comprises a gray code counter configured to provide a gray code signal to latch counter arrangements of the counter group. A PPL circuit comprises a gray code counter configured to generate a gray code signal used by a digital filter to adjust an oscillator. The gray code signal provides n-bit early/late information to the digital filter for adjustment of the oscillator.

A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.

A frequency divider circuit includes: a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divided clock signal; a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal; a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit.

A frequency divider circuit includes: a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divided clock signal; a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal; a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit.

A pulse density modulation method includes the following steps: S01, obtaining a number of bits n of a binary density value d, setting a number of bits of a counter as n, an initial value of the counter is 0 or 1; S02, searching for a rightmost 1: obtaining a number of bits j of the rightmost 1 of a current value i of the counter counted from right to left; a number in the counter is a binary number; a minimum value of j is 1; S03, determining whether corresponding bits are equal; S04, adding the value i of the counter by 1, proceeding to a next period, and turning to the step S02.

An event counter circuit can be configured to monitor operation of a system where a moving average register circuit can be configured to store a moving average value updated in each cycle of operation of the system by adding a number of system events occurring during a current cycle of the system operation to either 1) a current moving average value stored in the moving average register circuit or 2) a keep value generated by partitioning the current moving average value into the keep value and a transfer value representing system events not included in a determination of the moving average value for subsequent cycles of operation of the system

A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.