Systems, methods, and devices for encoding and decoding data packets for transmission across a data network. To encode, data packets are first subjected to a an outer code process to result in outer coded packets. The outer coded packets are then divided into generations or groups of outer coded packets, each group or generation having an equal number of packets. Output packets are then created by forming random linear combinations of the outer coded packets from a specific generation or group of outer coded packets. The coefficients for the various elements of each linear combination is selected from a Galois field of values. To decode the incoming packets, enough packets are received until an iterative decoding process can be initiated.

Various embodiments of methods and systems for closed loop multimode sleep clock frequency compensation in a portable computing device are disclosed. An exemplary embodiment leverages a modem to determine a frequency shift on a sleep clock signal when a reference clock has transitioned into a power saving mode. Using the frequency shift calculation, a compensation capacitor may be adjusted to deliver a more optimum dummy load on the crystal oscillator when the reference clock is taken offline. The method may iterate through until the actual frequency shift of the sleep clock is within an acceptable tolerance relative to zero and, further, may also set a status bit to indicate that the sleep clock frequency is stable.

A dual-frequency-output crystal controlled oscillator includes a crystal resonator, an oscillator circuit, a first output terminal, a second output terminal, and a selection circuit. The crystal resonator includes an input terminal for measurement and an output terminal for measurement. The oscillator circuit is configured to amplify an output of the crystal resonator; a first output terminal configured to output a first frequency based on an output from the oscillator circuit. The second output terminal is configured to output a second frequency lower than the first frequency based on the output from the oscillator circuit. The selection circuit is configured to turn on/off an output of the first frequency. The input terminal for measurement is disposed such that a distance between the input terminal for measurement and the second output terminal is longer than a distance between the input terminal for measurement and the first output terminal.

A dual-frequency-output crystal controlled oscillator includes a crystal resonator, an oscillator circuit, a first output terminal, a second output terminal, and a selection circuit. The crystal resonator includes an input terminal for measurement and an output terminal for measurement. The oscillator circuit is configured to amplify an output of the crystal resonator; a first output terminal configured to output a first frequency based on an output from the oscillator circuit. The second output terminal is configured to output a second frequency lower than the first frequency based on the output from the oscillator circuit. The selection circuit is configured to turn on/off an output of the first frequency. The input terminal for measurement is disposed such that a distance between the input terminal for measurement and the second output terminal is longer than a distance between the input terminal for measurement and the first output terminal.

A voltage controlled oscillator is provided. The voltage controlled oscillator includes a current controlled oscillator, a voltage to current conversion circuit and a noise cancellation circuit. The current controlled oscillator is configured to receive a bias current and generate an oscillating signal with an oscillating frequency according to the bias current. The voltage to current conversion circuit is coupled to a power supply voltage and configured to generate a supply current according to an input voltage. The noise cancellation circuit is configured to receive a bias voltage and the supply current from the voltage to current conversion circuit, and configured to generate a noise cancellation current in response to power supply voltage variation and cancel the noise cancellation current from the supply current to generate the bias current. The bias voltage of the noise cancellation circuit is coupled to an internal voltage of the voltage to current conversion circuit.

A voltage controlled oscillator is provided. The voltage controlled oscillator includes a current controlled oscillator, a voltage to current conversion circuit and a noise cancellation circuit. The current controlled oscillator is configured to receive a bias current and generate an oscillating signal with an oscillating frequency according to the bias current. The voltage to current conversion circuit is coupled to a power supply voltage and configured to generate a supply current according to an input voltage. The noise cancellation circuit is configured to receive a bias voltage and the supply current from the voltage to current conversion circuit, and configured to generate a noise cancellation current in response to power supply voltage variation and cancel the noise cancellation current from the supply current to generate the bias current. The bias voltage of the noise cancellation circuit is coupled to an internal voltage of the voltage to current conversion circuit.

A time synchronization device adapted for an electronic apparatus, an electronic apparatus, a time synchronization system and a time synchronization method. The time synchronization device includes: a signal generating circuit and a time adjusting circuit. The signal generating circuit includes: a control circuit, configured to generate a frequency control word; and a signal adjusting circuit, configured to receive the frequency control word and an input signal having an initial frequency, and to generate and output an output signal having a target frequency based on the frequency control word and the input signal. The time adjusting circuit is configured to perform a synchronization adjusting operation on a clock signal of the electronic apparatus based on the output signal having the target frequency.

Various embodiments relate to a bias generator including: a bias generator circuit; a master startup circuit that applies current to a first node in the bias generator circuit; a second startup circuit that applies current to additional nodes in the bias generator circuit; and a power switch that receives a power from a power supply and that provides power to the bias generator circuit, the master startup circuit, and the second startup circuit.

Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more TDC codes.

Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more TDC codes.