A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.

A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.

A frequency-locked loop (FLL) and a method for correcting an oscillation frequency of an output signal of the FLL are provided. The FLL includes a switched capacitor circuit, a first resistor set, a second resistor set, a determination circuit and a control circuit. The switched capacitor circuit includes a capacitor, and connection of the capacitor is switched according to the oscillation frequency. The first resistor set is configured to provide a first resistance, and the second resistor set is configured to provide a second resistance. The determination circuit is configured to generate a determination result according to the first resistance and the second resistance. The control circuit is configured to generate a control signal for correcting the first resistance and the second resistance according to the determination result, where the oscillation frequency is determined based on the capacitor and at least one of the first resistance and the second resistance.

An integrated circuit device, having functional circuitry driven by a clock signal, includes a first clock path for accepting an external clock signal where the first clock path includes first biasing circuitry configured to controllably pass the external clock signal, a second clock path for accepting an external frequency reference signal where the second clock path includes internal clock generation circuitry configured to generate an internal clock signal from the external frequency reference signal and second biasing circuitry configured to controllably pass the external frequency reference signal to the internal clock generation circuitry, and selector circuitry configured to select, based on user input, a clock output to drive the functional circuitry of the integrated circuit device. The clock output is selected from between (i) an output of the first clock path, and (ii) an output of the second clock path.

A device and method of clock synchronization for external memory interface. The device, and method, generating a clock output from a phase lock loop block via a sub-module clocking component; multiplexing the clock output through a global clock into different clock domains; clocking the data and an address or a command path by each clock domain; clocking the phase compensation FIFO by clock domain and clock phase alignment clock; generating the pointer for the phase compensation FIFO from central pointer generator block; and synchronizing the pointer of the adjacent intellectual property module with a parent intellectual property module.

First user equipment (UE) exchanges at least a portion of data to be transmitted to a communication network with a second UE on a side channel. The UEs then send the data to the network at increased transmission power by using transmit antennas of both the first and second UEs, instead of just those of the first UE. In some cases, the second UE may transmit a variation of the data sent by the first UE to perform transmit diversity and improve signal-to-noise ratio. To avoid unintended beamforming of the transmissions, the network may mix signals (e.g., having a same symbol) received at the same time period but at different sub-carriers, or mix the signals received at different time periods but at the same sub-carrier. The network may notify the UEs of a phase correction value based on the signals, and the UEs may adjust using the phase correction value.

The data recovery from sub-carriers gradients (DRSG) of a received OFDM signal affected by deterministic and random distortions introduced by a transmission link, contributes a method and a circuit for utilizing gradients characterizing shapes of OFDM sub-carriers comprised in such OFDM signal for recovering data symbols transmitted originally.

The data recovery from sub-carriers gradients (DRSG) of a received OFDM signal affected by deterministic and random distortions introduced by a transmission link, contributes a method and a circuit for utilizing gradients characterizing shapes of OFDM sub-carriers comprised in such OFDM signal for recovering data symbols transmitted originally.

A charge pump circuit includes: a charge pump core circuit configured to generate an output voltage, an oscillator configured to provide a clock signal for the charge pump core circuit, and a feedback circuit configured to control the oscillator based on the output voltage, wherein the feedback circuit includes an inner loop.

Described herein are systems, methods, and software to manage time calibration associated with an oscillator of a computing system. In one example, a computing system monitors clock cycles for an oscillator on the computing system, receives timing messages from a server, and calculates the frequency of the oscillator at intervals based on the monitored clock cycles and timing messages. The computing system further identifies a temperature from a temperature sensor at each of the intervals and generates a function to demonstrate frequency of the oscillator versus temperatures from the temperature sensor based on the identified temperatures and frequencies at the intervals.