Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.

An integrated circuit device, having functional circuitry driven by a clock signal, includes a first clock path for accepting an external clock signal where the first clock path includes first biasing circuitry configured to controllably pass the external clock signal, a second clock path for accepting an external frequency reference signal where the second clock path includes internal clock generation circuitry configured to generate an internal clock signal from the external frequency reference signal and second biasing circuitry configured to controllably pass the external frequency reference signal to the internal clock generation circuitry, and selector circuitry configured to select, based on user input, a clock output to drive the functional circuitry of the integrated circuit device. The clock output is selected from between (i) an output of the first clock path, and (ii) an output of the second clock path.

Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

A method for measuring asynchronous timestamp requests includes receiving a timestamp (“TS”) request from a client device during a first interval of a time of day (“TOD”) clock, and calculating, using the TOD clock, at a next interval of the TOD clock, a TS correction of the TS request relative to a reference point of the first TOD clock interval. The method further includes adding the TS correction to the reference point of the first interval of the TOD clock, and outputting the corrected TS to the client device.

Various embodiments relate to a free running oscillator, including: a voltage controlled oscillator circuit including an input configured to receive an input voltage and an output configured to provide an oscillation signal, wherein the input voltage controls a frequency of the oscillation signal; a frequency to voltage circuit including an input configured to receive the oscillation signal and an output configured to produce a voltage dependent on a frequency of the oscillation signal; a comparison circuit including an input and an output comprising: a first amplifier including a first input, a second input, and an output, wherein the output is based upon a difference in voltage between the first input and the second input, wherein the first input received one of a reference voltage and the output of frequency to voltage circuit; a second amplifier including a first input, a second input, and an output, wherein the output is based upon a difference in voltage between the first input and the second input, first input is connected to the comparator output, the second inputs is connected to the second amplifier output; a sampling capacitor connected between the second input of the first amplifier and a ground; and an integration capacitor connected between the comparator output and the ground.

A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.

A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.

A sensor device has a clock generator, a counter, an exciter device, a sensor element and an evaluation device, and outputs a sensor signal in response to a request signal having alternating leading and trailing edges. The counter reading is incremented differently, depending on whether the request signal has a leading/trailing edge between two successive leading or trailing edges of the clock signal. If the request signal has such a leading/trailing edge the counter corrects the counter reading. The value of the excitation signal outputted by the exciter device depends on the counter reading or a value derived therefrom. The sensor element outputs based on the excitation signal a raw signal, which is supplied to the evaluation device. The evaluation device determines based on this information whether to acquire the raw signal and how to take the raw signal into account when establishing the sensor signal.

A sensor device has a clock generator, a counter, an exciter device, a sensor element and an evaluation device, and outputs a sensor signal in response to a request signal having alternating leading and trailing edges. The counter reading is incremented differently, depending on whether the request signal has a leading/trailing edge between two successive leading or trailing edges of the clock signal. If the request signal has such a leading/trailing edge the counter corrects the counter reading. The value of the excitation signal outputted by the exciter device depends on the counter reading or a value derived therefrom. The sensor element outputs based on the excitation signal a raw signal, which is supplied to the evaluation device. The evaluation device determines based on this information whether to acquire the raw signal and how to take the raw signal into account when establishing the sensor signal.