An apparatus and a method. The apparatus includes a delay processor, a coarse converter and node selector connected to the delay processor and configured to select a first voltage V.sub.1 and a second voltage V.sub.2 of opposite polarities of adjacent stages of the delay processor, a fine converter connected to the coarse converter and node selector and configured to determine a zero-crossing time associated with the first voltage V.sub.1 and the second voltage V.sub.2; and an encoder connected to the coarse converter and the fine converter and configured to receive and encode the first voltage V.sub.1, the second voltage V.sub.2 and the zero-crossing time, wherein V.sub.1 is a first negative voltage before the zero-crossing time, and V.sub.2 is a first positive voltage after the zero-crossing time.

The present disclosure provides a signal conversion circuit and fingerprint identification system. The signal conversion circuit is configured to generate a first digital signal according to a first analog signal, and includes a comparator and counter. The comparator includes a first input terminal configured to receive the first analog signal, a second input terminal connected to a reference voltage generator and configured to receive a reference voltage, and an output terminal configured to output a second digital signal. The counter is connected to the output terminal, and is configured to generate a first digital signal. The signal conversion circuit according to the present disclosure has the advantages of simple circuit structure, small circuit area, low cost and low power consumption.

First and second p-type transistors are connected in series between an output terminal and a positive power terminal. First and second n-type transistors are connected in series between a node and a negative power terminal. A third p-type transistor is connected between a node and the positive power terminal. Third and fourth n-type transistors are connected in series between the output terminal and a low potential terminal. Fourth and fifth p-type transistors are connected in series between a node and the negative power terminal. A fifth n-type transistor is connected between a node and the negative power terminal. A high potential is outputted without leak current when the first to fifth p-type transistors are turned on and the first to fifth n-type transistors are turned off.

First and second p-type transistors are connected in series between an output terminal and a positive power terminal. First and second n-type transistors are connected in series between a node and a negative power terminal. A third p-type transistor is connected between a node and the positive power terminal. Third and fourth n-type transistors are connected in series between the output terminal and a low potential terminal. Fourth and fifth p-type transistors are connected in series between a node and the negative power terminal. A fifth n-type transistor is connected between a node and the negative power terminal. A high potential is outputted without leak current when the first to fifth p-type transistors are turned on and the first to fifth n-type transistors are turned off.

An optical network includes a transmitting portion configured to (i) encode an input digitized sequence of data samples into a quantized sequence of data samples having a first number of digits per sample, (ii) map the quantized sequence of data samples into a compressed sequence of data samples having a second number of digits per sample, the second number being lower than the first number, and (iii) modulate the compressed sequence of data samples and transmit the modulated sequence over a digital optical link. The optical network further includes a receiving portion configured to (i) receive and demodulate the modulated sequence from the digital optical link, (ii) map the demodulated sequence from the second number of digits per sample into a decompressed sequence having the first number of digits per sample, and (iii) decode the decompressed sequence.

An analog-to-digital converter arrangement may include an analog amplifier with variable gain; an analog-to-digital converter; a digital reconstruction element including elements to reduce an influence of transients during a change of the variable gain of the analog amplifier.

One example includes a pipelined analog-to-digital converter device. The pipelined analog-to-digital converter device includes a capacitive digital-to-analog converter, a first analog-to-digital converter, and a second analog-to-digital converter. The capacitive digital-to-analog converter includes a capacitor comprised of a top plate and a bottom plate, the capacitive digital-to-analog converter sampling an analog input signal applied to the pipelined analog-to-digital converter device while the capacitor is grounded, holding the sampled analog input while the top plate is floated, and outputting a residue voltage. The second analog-to-digital converter is coupled to the top plate of the capacitor, the second analog-to-digital converter producing a second digital representation of voltage on the top plate of the capacitor after the top plate is floated, wherein the second digital representation represents fine bits produced by the first stage of the pipelined analog-to-digital converter device.

Improved mechanisms for applying noise-shaped segmentation techniques in a multi-bit DAC are disclosed. Noise-shaped segmentation refers to constructing two or more noise-shaped signals whose sum equals the original digital input signal by splitting each word of the input signal into two or more sub-words and converting each sub-word by a respective sub-word DAC group. Disclosed mechanisms include determining a range of amplitudes of a portion of the input signal over a certain time period, and, when converting digital words of that portion to analog values, limiting the number of sub-word DAC groups which are used for the conversion only to a number that is necessary for generating an analog output corresponding to the portion being evaluated, which number is determined based on the tracked amplitudes and could be smaller than the total number of sub-word DAC groups. Placing unused sub-word DAC groups into a power saving mode reduces power consumption.

An apparatus includes a processor, a Phase-Locked Loop Waveform Generator (PLLWG), a Voltage Controlled Oscillator (VCO), a demodulator, signal conditioning circuitry, and an Analog-to-Digital Converter (ADC). The processor generates control command signals, receives a digital data input signal, and performs spectrum analysis on the digital data input signal. The PLLWG is coupled to the processor, receives the control command signals, and generates a charge pump output signal based on the control command signals. The VCO is coupled to the PLLWG, receives a tuning signal based on the charge pump output signal, and outputs a VCO output signal based on the tuning signal. The demodulator receives an incoming modulated signal and the VCO output signal, and outputs an analog output signal based on the incoming modulated signal and the VCO output signal. The ADC converts the analog output signal into the digital data input signal.

Methods and devices for an energy efficient digital to analog conversion are disclosed. With the achievable sampling rates and output voltage levels, high power RF signals can be synthesized. A plurality of pulses are generated and coupled onto transmission lines. On the other end of the transmission line the pulses are either reflected or transmitted to a load line depending on the status of a termination element. In one embodiment the reflected pulses are collected and sent to a load. The energy in the transmitted pulses can be recovered and reused. In another embodiment the transmitted pulses are collected and transmitted to a load and the energy in the reflected pulses is recovered and reused.