A voltage or current regulator has a power DAC and ADC in a negative feedback loop, locked to a reference voltage or current. The ADC may have one or more parallel comparators followed by one or more parallel filters. The regulator may include a multiplexer to select between filter output signals and to forward the selected signal to the power DAC. The regulator may receive power management mode control codes to modify filter behavior and/or to select between multiple parallel filters. By modifying the loop behavior, the regulator is able to swiftly change between power management modes supporting different power level and noise profiles. Regulators with a single comparator can lock the output to a single reference voltage or current. Regulators with two comparators can regulate the output to vary within a range limited by an upper and a lower reference voltage or current.

In a system for converting digital data into a modulated optical signal, an electrically controllable device, including a modulator having one or more actuating electrodes, provides an analog-modulated optical signal that is modulated in response to output data bits of a digital-to-digital mapping. A digital-to-digital conversion provides the mapping of input data words to the output data bits. The mapping enables adjustments to correct for non-linearities and other undesirable characteristics, thereby improving signal quality.

Circuit and method for encoding an analog signal to a stream of bits at an Analog to Digital Converter (ADC) and subsequent reconstruction of the original signal from the bit stream at a Digital to Analog Converter (DAC), where the ADC module samples the analog signal at a sub-Nyquist rate and encodes the samples to a stream of bits. The bit steam is subsequently used to reconstruct the Nyquist-rate samples of the original analog signal at the DAC. The ADC samples the input signal in one of the two realizations of non-uniform sampling, namely, Random Sampling (RS) and Level Crossing (LC) sampling techniques, according to embodiments of the disclosed invention.

Circuit and method for encoding an analog signal to a stream of bits at an Analog to Digital Converter (ADC) and subsequent reconstruction of the original signal from the bit stream at a Digital to Analog Converter (DAC), where the ADC module samples the analog signal at a sub-Nyquist rate and encodes the samples to a stream of bits. The bit steam is subsequently used to reconstruct the Nyquist-rate samples of the original analog signal at the DAC. The ADC samples the input signal in one of the two realizations of non-uniform sampling, namely, Random Sampling (RS) and Level Crossing (LC) sampling techniques, according to embodiments of the disclosed invention.

In one form, a signal chain circuit includes a signal chain processing circuit between an input for receiving a differential input signal having a first common-mode voltage, and an output for providing a differential output signal having a second, different common-mode voltage. It includes an amplifier with a differential output stage coupled to a differential input stage and having positive and negative output terminals forming its output, and positive and negative feedback terminals. The differential output stage provides a first voltage drop between the positive output terminal and the positive feedback terminal, and a second voltage drop between the negative output terminal and the negative feedback terminal. The common-mode feedback circuit regulates a common-mode voltage between the positive and negative feedback terminals to the second common-mode voltage. In another form, an analog-to-digital converter includes a range extending logic circuit to extend the range of a ring oscillator based analog-to-digital converter.

An electrocardiogram (ECG) signal processing system is provided. The ECG signal processing system comprises an analog-to-digital converter (ADC) configured to convert an input analog ECG signal into a digital ECG signal, and a digital signal processing engine (DSPE) coupled to the ADC to receive the digital ECG signal. The DSPE is configured to decompose and reconstruct the digital ECG signal. A dynamic system clock source is coupled to the ADC and the DSPE for dynamic signal sampling, the dynamic system clock source clocking the ADC and the DSPE at a first frequency f1 to detect one or more first parameters of the input analog ECG signal and at a second frequency f2 to detect one or more second parameters of the input analog ECG signal.

A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.

In accordance with embodiments of the present disclosure, a processing system may include multiple selectable processing paths for processing an analog signal in order to reduce noise and increase dynamic range. Techniques are employed to transition between processing paths and calibrate operational parameters of the two paths in order to reduce or eliminate artifacts caused by switching between processing paths.

A method of increasing SAR ADC conversion rate and reducing power consumption by employing a new timing scheme and minimizing timing delay for each bit-test during binary-search process. The high frequency clock input requirement is eliminated and higher speed rate can be achieved in SAR ADC.

The image sensor includes a first analog-to-digital converter configured to convert a first analog pixel signal output from a first pixel in a row into first digital signals, a second analog-to-digital converter configured to convert a second analog pixel signal output from a second pixel in the row into second digital signals, a first output circuit configured to output a first bit value at a first position in the first digital signals in response to a first enable control signal, and a second output circuit configured to output a second bit value at a second position in the second digital signals in response to a second enable control signal, the second position in the second digital signals corresponding to the first position in the first digital signals, wherein the second enable control signal is activated with a delay from the activation of the first enable control signal.