The image sensor includes a first analog-to-digital converter configured to convert a first analog pixel signal output from a first pixel in a row into first digital signals, a second analog-to-digital converter configured to convert a second analog pixel signal output from a second pixel in the row into second digital signals, a first output circuit configured to output a first bit value at a first position in the first digital signals in response to a first enable control signal, and a second output circuit configured to output a second bit value at a second position in the second digital signals in response to a second enable control signal, the second position in the second digital signals corresponding to the first position in the first digital signals, wherein the second enable control signal is activated with a delay from the activation of the first enable control signal.

A pipelined SAR ADC includes a first stage and passive residue transfer is used to boost a conversion speed. Owing to the passive residue transfer, the first stage may be released during a residue amplification phase, cutting down a large part of the first-stage timing budget. An asynchronous timing scheme may also be adopted in both the first- and second-stage SAR ADCs to maximize the overall conversion speed. Lastly, a dynamic amplifier with proposed PVT stabilization technique may be employed to further save power consumption and improve the conversion speed simultaneously.

The present disclosure describes aspects of current removal for digital-to-analog converters (DACs). In some aspects, a circuit for converting a digital input to an analog output includes a first resistor ladder having first resistors connectable to respective current sources and connected to a first output of the circuit. The circuit also includes second resistor ladder having second resistors connectable to the respective current sources and connected to a second output of the circuit. A common node is formed between common resistor terminals of the first resistor ladder and the second resistor ladder. Current removal circuitry is connected to the common node and referenced to an amount of current provided by the respective current sources. By removing current from the common node of the resistor ladders, common-mode current at outputs of the circuit can be reduced with minimal degradation of differential performance of the circuit.

A time register includes: a pair of inputs coupled to a pair of input clocks; a pair of tri-state inverters for producing a pair of level signals; and a pair of outputs coupled to the level signals for producing a pair of output clocks, wherein the tri-state inverters are responsive to a pair of state signals and the pair of input clocks for holding or discharging the level signals.

A digital-to-analog converter including a resistor string configured to provide a plurality of gradation voltages formed by receiving a top voltage at one end thereof and a bottom voltage at the other end; a plurality of pass transistors including a pass transistor having one end which is electrically connected to the resistor string and outputting any one among the plurality of gradation voltages; and a decoder configured to control the plurality of pass transistors. The plurality of the pass transistors are included in any one among a plurality of groups according to values of the gradation voltages, and the pass transistors included in the any one group are divided into a first group and a second group according to output gradation voltages, and pass transistors included in the first group and pass transistors included in the second group are different types of pass transistors.

Digital focal plane arrays (DFPAs) with multiple counters per unit cell can be used to convert analog signals to digital data and to filter the digital data. Exemplary DFPAs include two-dimensional arrays of unit cells, where each unit cell is coupled to a corresponding photodetector in a photodetector array. Each unit cell converts photocurrent from its photodetector to a digital pulse train that is coupled to multiple counters in the unit cell. Each counter in each unit cell can be independently controlled to filter the pulse train by counting up or down and/or by transferring data as desired. For example, a unit cell may perform in-phase/quadrature filtering of homodyne- or heterodyne-detected photocurrent with two counters: a first counter toggled between increment and decrement modes with an in-phase signal and a second counter toggled between increment and decrement modes with a quadrature signal.

An apparatus and method is disclosed with embodiments of a: 1. digital to analog and reference time converter; 2. analog and reference time to digital converter; 3. Sheahan non-linear time-varying, analog and digital control system; and 4. Sheahan Communication Channel are described in detail herein. Some embodiments use time stamp having 72 bits of time data sufficient to identify each clock pulse of a 9.192631770 GHz clock signal plus an additional 8 bits representing 2.sup.8=256 interpolated clock phases in order reach a resolution of approximately 0.425 picoseconds per clock phase. Thus an 80 bit time stamp is generated and used as described herein.

A method can include modulating an amplified analog signal into a digital data stream, filtering the digital data stream with a first filter, generating gain control values associated with amplified analog signal based on the filtered data stream with the first filter and filtering the digital data stream with a second filter, and generating output digital values associated with the amplified analog signal based on the filtered data stream with the second filter. Corresponding systems and devices are also disclosed.

A first capacitor and a second capacitor are each arranged such that their first ends are coupled to a first node. A first switch is arranged between a second end of the first capacitor and a high voltage terminal. A second switch is arranged between the second end of the second capacitor and a low voltage terminal. A fifth switch is arranged between the second end of the first capacitor and a first input of a comparator. A sixth switch is arranged between the second end of the second capacitor and the first input of the comparator.

There is disclosed herein charge-mode circuitry for use in a comparator to capture a difference between magnitudes of first and second input signals, the circuitry comprising: a tail node configured during a capture operation to receive a charge packet; first and second nodes conductively connectable to said tail node along respective first and second paths; and control circuitry configured during the capture operation to control such connections between the tail node and the first and second nodes based on the first and second input signals such that said charge packet is divided between said first and second paths in dependence upon the difference between magnitudes of the first and second input signals.