An interface circuit includes an input circuit. The input circuit includes a first input pin, a second input pin and a third input pin. The input circuit further includes a first operational amplifier including a first output pin, a first non-inverting input pin electrically coupled to the first input pin via a first impedance and a first switch, and a first inverting input pin coupled to the first output pin. The input circuit also includes a second operational amplifier including a second output pin, a second non-inverting input electrically coupled to the second input pin via a second impedance and a second inverting input pin electrically coupled to the third input pin via a third impedance and a second switch. The first input pin and the second input pin are electrically coupled via a third switch and a fourth impedance.

A solar cell power conversion device is disposed between a solar cell and a consumer premises distribution system. A storage battery power conversion device is disposed between a storage battery and the consumer premises distribution system. When an AC effective voltage in the consumer premises distribution system deviates from a voltage range defined in accordance with dead zone information transmitted from HEMS, system voltage stabilization control for returning the AC effective voltage to fall within the voltage range is performed by control of active power and reactive power that are output from a first DC/AC conversion circuit and a second DC/AC conversion circuit.

A circuit having an array of Analog-to-Digital Converters (ADCs); a sampling order selector configured to select a sampling order of the ADCs and output corresponding sampling order control words; sampling pulse generators coupled between the sampling order selector and the respective ADCs, and configured to output respective sampling pulses based on the respective sampling order control words, wherein the ADCs are configured to sample and convert analog data into digital data in response to the sampling pulses; and a single clock generator configured to distribute a delay-matched clock to each of the ADCs in parallel, to each of the sampling pulse generators in parallel, and to the sampling order selector.

A reference voltage generator comprises a comparator, a digital-to-analog converter (DAC) and a switched capacitor accumulator. The comparator receives a reference voltage input, a feedback input, and a control signal. The DAC is coupled to an output of the comparator, and the switched capacitor accumulator is coupled to an output of the DAC. In some implementations, a digital filter is coupled between the output of the comparator and the input of the DAC. The switched capacitor accumulator can be coupled to a buffer that outputs the feedback input and a reference voltage for an analog-to-digital converter (ADC). In some implementations, the feedback loop includes N one-bit DACs coupled to the output of the comparator and N switched capacitor accumulators, each of which is coupled to a unique one-bit DAC.

A serial data receiver circuit included in a computer system may include a front-end circuit, a sample circuit that includes multiple analog-to-digital converter circuits, and a recovery circuit. The front-end circuit may generate an equalized signal using multiple signals that encode a serial data stream of multiple data symbols. Based on a baud rate of the serial data stream, a determined number of the multiple analog-to-digital converter circuits sample, using a recovered clock signal, the equalized signal at the respective times to generate corresponding samples. The recovery circuit generates, using the samples, the recovered clock signal and recovered data symbols.

An analog-to-digital converter (1) includes an S/H circuit (10) configured to sample and hold an analog input signal (IN) in synchronization with a sampling clock signal (CLK), a delay circuit (20) configured to delay the sampling clock signal (CLK), an ADC circuit (30) configured to sample an output signal (S/H_out) of the S/H circuit (10) in synchronization with the sampling clock signal (CLK_delay) that is delayed, and output a digital signal (OUT) corresponding to an amplitude of the output signal that is sampled, and a delay adjustment circuit (40) configured to adjust a delay time of the sampling clock signal (CLK) in the delay circuit (20) in accordance with a change in frequency of the sampling clock signal (CLK).

A control system includes: a semiconductor chip, having built therein a processing part, an A/D converter and a pull device circuit; a wiring part, having one end connected to a terminal connected to the A/D converter; and a sensor, connected to the other end of the wiring part and inputting a sensor signal in analog form via the wiring part. The pull device circuit includes a switching element, and has one end connected to ground or a power supply voltage and the other end connected between the A/D converter and the terminal. The processing part includes: a switch control part, controlling the switching element to be in an on or off state; a sensor information generator, generating sensor information based on the sensor signal; and a disconnection detector, detecting disconnection of the wiring part based on output of the A/D converter when the switching element is in the on state.

A semiconductor device with a novel structure is provided. The semiconductor device includes a sensor, an amplifier circuit to which a sensor signal of the sensor is input, a sample-and-hold circuit that retains a voltage corresponding to an output signal of an amplifier input to the sample-and-hold circuit, an analog-to-digital converter circuit to which an output signal of the sample-and-hold circuit corresponding to the voltage is input, and an interface circuit. The interface circuit has a function of switching and controlling a first control period in which the sensor signal is input to the amplifier circuit and an output signal of the amplifier circuit is retained in the sample-and-hold circuit and a second control period in which a digital signal obtained by output of the voltage retained in the sample-and-hold circuit to the analog-to-digital converter circuit is output to the interface circuit. In the first control period, the analog-to-digital converter circuit is switched to stop output of the digital signal. The first control period is longer than the second control period.

A system and method for performing discrete frequency transform including a pair of single-bit analog to digital converters (ADCs), a phase converter, a memory, a discrete frequency transform converter and summation circuitry. The ADCs convert an analog input signal into N pairs of binary in-phase and quadrature component samples each being one of four values at a corresponding one of four phases. The phase converter determines a phase value for each pair of component samples. The memory stores a set of discrete frequency transform coefficient values based on N. The discrete frequency transform converter uses a phase value and a pair of discrete frequency transform coefficient values retrieved from the memory for a selected frequency bin to determine a discrete frequency component for each pair of phase component samples. The summation circuitry sums the corresponding N frequency domain components for determining a frequency domain value for the selected frequency bin.

“An image sensing device is provided in the present invention. A control circuit determines a voltage change rate of a sensing signal according to a voltage value of the sensing signal generated by a light sensing unit during an estimation period, and controls an input adjustment circuit during an exposure period according to the voltage change rate to provide an input adjustment signal to a negative input end of an operational amplifier, such that a signal value of an amplified signal falls within a pre-set range during the exposure period.”