A device and method of an image processing system where a Field Sequential Color Delta Sigma Pulse Density Modulation is used for digital displays, where the digital displays are non-emissive. The device and method are a digital driving solution using Delta Sigma Encoding where N bit-per-component symbols at F1 frame-rate-per-second are represented using M bits-per-component symbols at F2 frame-rate-per-second, where N≥M and F2≥F1. The F2 frames are sent to a sequential color picker, which outputs frames with one color, followed by the next in a sequential pattern which reduces power consumption, increases color saturation, increases contrast, and increases brightness.

A filter system includes: a first mixer, converting an input signal into a first signal according to a reference frequency signal, wherein the reference frequency signal corresponding to a target frequency band; an analog-to-digital converter, coupled to the first mixer, converting the first signal into a first digital signal; a digital filter, coupled to the analog-to-digital converter, filtering the first digital signal according to a first frequency band and generating a second digital signal, wherein the first frequency band corresponding to the first signal; a digital-to-analog converter coupled to the digital filter, converting the second digital signal into a second signal; and a second mixer, coupled to the digital-to-analog converter, converting the second signal into an output signal according to the reference frequency signal, wherein the output signal corresponds to the input signal filtered by the target frequency band.

A delta-sigma modulation type A/D converter includes: a capacitively coupled amplifier having a sampling capacitor, a feedback capacitor, and an amplifier; a correlated double sampling type first integrator as a first-stage integrator, which is connected to the capacitively coupled amplifier without a switch; a second integrator arranged after the first integrator; a quantizer arranged after the second integrator and quantizing an output of the second integrator; and an D/A converter that D/A-converts an output of the quantizer and feeds back to any one of the capacitively coupled amplifier, the first integrator, and the second integrator.

Provided is a delta-sigma modulator including a first integral unit configured to integrate an input analog signal, a second integral unit configured to integrate a signal output by the first integral unit, a quantizer configured to quantize a signal output by the second integral unit, a DA converter configured to perform DA conversion on an output of the quantizer and output a feedback signal to be fed back to the first integral unit, and a control unit configured to perform control to cause the first integral unit and the second integral unit to perform different integral operations during a first period and a second period, in which the second integral unit is configured to receive the feedback signal output by the DA converter via the first integral unit and integrate the feedback signal during the first period and the second period.

In one embodiment, a method for converting an input digital signal into an analog signal is provided. The method comprises modulating the input digital signal into a modulated digital signal, and converting the modulated digital signal into the analog signal using a digital-to-analog converter (DAC). The modulation shapes quantization noise of the DAC to place a notch at a frequency within an out-of-bound frequency band to reduce the quantization noise within the out-of-bound frequency band.

A cellular radio architecture that includes a multiplexer coupled to an antenna structure and including multiple signal paths, where each signal path includes a bandpass filter that passes a different frequency band than the other bandpass filters and a circulator that provides signal isolation between the transmit signals and the receive signals. The architecture also includes a receiver module having a separate signal channel for each of the signal paths in the multiplexer, where each signal channel in the receiver module includes a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal. The delta-sigma modulator includes an LC filter having a plurality of LC resonator circuits, a plurality of transconductance amplifiers and a plurality of integrator circuits, where a combination of one resonator circuit, transconductance amplifier and integrator circuit represents a two-order stage of the LC filter.

A DAC circuit includes: a PWM encoding circuit for converting a digital signal to first and second PWM signals, whereby a combination of the first and second PWM signals becomes a PWM encoded signal of at least 3 levels including a positive, a zero and a negative level, wherein the digital signal represents a number in a numerical range; and a demodulation circuit for generating the analog signal according to the first and second PWM signals. The first and second PWM signals have a minimum duty larger than 0 when the digital signal represents a middle number in the numerical range. The zero level of the combination of the first and second PWM signals has a duty which decreases as a difference between the number represented by the digital signal and the middle number increases.

A device includes a phase detector circuit, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector circuit detects a clock skew between a reference signal and an input signal. The charge pump circuit translates the clock skew into a voltage. A sample and hold circuit samples the voltage, at a first time, and maintain the sampled voltage until a second time. The comparator (i) detects a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjustment of the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit.

An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspect of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor to form an analog multiplication product as a charge applied to the differential charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.

A delta-sigma beamformer includes a beamsummer and a plurality of delta-sigma modules. Each of the delta sigma modules includes a delta-sigma modulator configured to receive analog ultrasound signals from one or more transducer elements and output a delay line including a plurality of samples based on the analog ultrasound signals. Each delta-sigma modulator includes a comb filter connected to the delta-sigma modulator and configured to output a difference between two of the plurality of samples in the delay line. Each delta-sigma modulator includes an accumulator module. Each accumulator module includes an accumulator connected to the comb filter. Each accumulator module is configured to integrate signals received from the comb filter during a non-delay-expansion period and transmit the integrated signals to the beamsummer during the non-delay-expansion period. Each accumulator module is configured to output a zero to the beamsummer during a delay-expansion period.