A signal processing circuit includes: a plurality of A/D conversion units of a plurality of channels, each of plurality of the A/D conversion units including an amplifier configured to amplify an input analog signal and an A/D converter configured to convert an output signal from the amplifier into a digital signal, wherein at least one of operation parameters of the amplifier and the A/D converter is set individually for each of the plurality of channels.

A wide band continuous time delta-sigma modulator implements a time interleaved quantization processing operation. The modulator may provide for an inherent finite impulse response filtering in the feedback loop. Additionally, further finite impulse response filtering in each time interleaved feedback path may be provided.

A built-in self-test (BIST) circuit is provided for testing an analog-to-digital converter (ADC). A multi-order sigma-delta (ΣΔ) modulator has an input that receives an input signal, a first output generating analog test signal derived from the input signal and applied to an input of the ADC and a second output generating a binary data stream. A digital recombination and filtering circuit has a first input that receives the binary data stream and a second input that receives a digital test signal output from the ADC in response to the analog test signal. The digital recombination and filtering circuit combines and filters the binary data stream and digital test signal to generate a digital result signal including a signal component derived from an error introduced by operation of the ADC. A correlation circuit is used to isolate that error signal component.

A sigma-delta modulation device includes a detection circuit and a sigma-delta modulator. The detection circuit is configured to detect an input signal to generate a detection signal, and compare the detection signal and a threshold to generate a control signal. The sigma-delta modulator is coupled to the detection circuit and configured to store a plurality of noise transfer functions, select one of the noise transfer functions according to the control signal, and convert the input signal into an output signal according to the noise transfer function.

During a sampling phase, an analog front end circuit connects input of a first sampling capacitor to an analog input signal and input of a second sampling capacitor to a reference signal, and connects first and second hold capacitors to ground. During a partial tracking phase, input of the first sampling capacitor is connected to the reference voltage and the input of the second sampling capacitor is connected to the analog input signal. The first hold capacitor is connected to a first output of a gain amplifier and the second hold capacitor to a second output of the gain amplifier. Output of the first sampling capacitor is coupled to a first input of an amplifier and output of the second sampling capacitor is coupled to a second input of the amplifier.

The present invention relates to a method for adjusting the resonance frequency of a loop filter in a delta-sigma modulator, e.g. in an angular rate sensor, to a predetermined frequency value, wherein the sigma-delta modulator comprises an input terminal, which is connected to the loop filter, a quantizer, which is connected to an output of the loop filter, and a feedback branch, which couples an output of the quantizer back to the input terminal. The method comprises the following steps: Optional rough adjustment of the resonance frequency of the filter by means of the regulating variable of a second oscillator, input of a filter input signal of the loop filter into a frequency adjustment circuit, determination of a noise spectrum of the filter input signal in a first frequency band and a second frequency band, wherein the first frequency band and the second frequency band are arranged symmetrically around the predetermined frequency, comparison of the noise spectra and creation of an adjustment signal that leads to a frequency adjustment when the noise spectra deviate from one another, and feedback of the adjustment signal of the frequency adjustment circuit to a control input of the loop filter for setting the filter frequency in response to the comparative result.

Systems and method for improving stability and performance in class-D modulators. In particular, a multi-cycle feedback network is positioned around a quantizer of a digital class-D amplifier. The multi-cycle feedback network allows the main class-D feedback loop to have multiple clock cycles of delay.

A network device may receive a signal from a headend, wherein a bandwidth of the received signal spans from a low frequency to a high frequency and encompasses a plurality of sub-bands. The network device may determine, based on communication with the headend, whether one of more of the sub-bands residing above a threshold frequency are available for carrying downstream data from the headend to the circuitry. The network device may digitize the signal using an ADC operating at a sampling frequency. The sampling frequency may be configured based on a result of the determining. When the sub-band(s) are available for carrying downstream data from the headend to the network device, the sampling frequency may be set to a relatively high frequency. When the sub-band(s) are not available for carrying downstream data from the headend to the network device, the sampling frequency may be set to a relatively low frequency.

This application relates to analogue-to-digital converters (ADCs). An ADC 200 has a first converter (201) for receiving an analogue input signal (AIN) and outputting a time encode signal (DT), such as a pulse-width-modulated (PWM) signal, based on input signal and a first conversion gain setting (GIN). In some embodiments the first converter has a PWM modulator (401) for generating a PWM signal such that the input signal is encoded by pulse widths that can vary continuously in time. A second converter (202) receives the time encoded signal and outputs a digital output signal (DOUT) based on the time encoded signal (DT) and a second conversion gain setting (GO). The second converter may have a first PWM-to-digital modulator (403). A gain allocation block (204) generates the first and second conversion gain settings based on the time encoded signal (DT). The gain allocation block (204) may have a second PWM-to-digital modulator (203) which may be of lower latency and/or lower resolution that the first PWM-to-digital modulator (403).

In accordance with an embodiment, a method of operating an oversampled data converter having a switched-capacitor (SC) integrator includes operating the oversampled data converter in a gain calibration mode; applying a first voltage to a feedback port of the SC integrator to form a feedback voltage, and during a first clock phase the method further includes applying the first voltage to a first series capacitor via the input port when an output of the oversampled data converter is in a first state; applying a bypass voltage to the first series capacitor when the output of the oversampled data converter is an a second state and applying the first voltage to a second series capacitor via the feedback port with a polarity based on the output of the oversampled data converter, and during a second clock phase the method includes integrating charges of the first series capacitor and the second series capacitor.