An Artificial Neural Network (ANN) processing system includes artificial neurons (processing elements) and an analog to digital converter (ADC). An artificial neuron includes a digital to analog converter (DAC) and a low pass filter (LPF) configured to generate a first filtered analog current signal. Also, the artificial neuron includes a delta-sigma DAC configured to generate an M-bit current signal based on a digital weight value. The artificial neuron also includes a multiplier configured to generate a first output current source signal based on the first filtered analog current signal and the M-bit current signal. The ADC is operably coupled to a common node via a single line and configured to generate a digital output signal based on an input voltage of the ADC. The digital output signal is representative of a summation of output analog current signals at a common node to which the ADC is operably coupled.

The number of bits in the quantizer can be decoupled from the number of bits in the feedback digital-to-analog converter (DAC). A delta-sigma analog-to-digital converter circuit can include a first quantizer to generate an output having a first number of bits and a second quantizer coupled to an output of the first quantizer, where the second quantizer can receive the output of the first quantizer and generate an output having a second number of bits. The feedback DAC can be coupled to the second quantizer to receive a representation of the output of the second quantizer, where the output of the feedback digital-to-analog converter circuit has the second number of bits. These techniques can reduce the area of the feedback DAC, e.g., 4 or 5 bits, and the techniques can achieve a higher maximum stable amplitude (MSA) because it is effectively a second order loop.

A digital filter is used in an A/D converter and includes a first filter and second filter. The first filter outputs first digital data by performing filter processing on output of an A/D conversion unit included in the A/D converter. The second filter outputs second digital data by performing filter processing on the output of the A/D conversion unit. The second digital data has either a lower resolution or a smaller effective number of bits than the first digital data does. The second filter outputs the second digital data before the first filter outputs the first digital data.

An analog-to-digital converter (ADC) includes a modulator, an integrator circuit, and first and second differentiator circuits. The modulator has a modulator input and a modulator output. The modulator input is configured to receive an analog signal, and the modulator is configured to generate digital data on the modulator output. The integrator circuit has an integrator circuit input and an integrator output. The integrator input is coupled to the modulator output. The first differentiator circuit is coupled to the integrator output, and the first differentiator circuit is configured to be clocked with a first clock. The second differentiator circuit is coupled to the integrator output, and the second differentiator circuit configured to be clocked with a second clock. The second clock is out of phase with respect to the first clock.

Current Wireless transmission volume is such that techniques to compress transmitted data is the object of ongoing technical enhancements. The Invention consists of methods of using rapid changes in signal voltage to convey additional data which may be used for Data Compression, Encryption, and other purposes. They include varying amounts of change referred to as Encode Amplitude (EA) and Baseline Modulation (BM) using a change down to baseline voltage,

Current Wireless transmission volume is such that techniques to compress transmitted data is the object of ongoing technical enhancements. The Invention consists of methods of using rapid changes in signal voltage to convey additional data which may be used for Data Compression, Encryption, and other purposes. They include varying amounts of change referred to as Encode Amplitude (EA) and Baseline Modulation (BM) using a change down to baseline voltage,

A power supply monitor includes a delta-sigma modulator including an input receiving a binary number and an output providing a pulse-density modulated signal, the delta-sigma modulator operable to scale the pulse-density modulated signal based on the binary number. A fast droop detector circuit includes a level shifter providing the modulated signal referenced to a clean supply voltage. A lowpass filter is coupled between the level shifter and a comparator. The comparator produces a droop detection signal at said output responsive to a monitored supply voltage dropping below a predetermined level relative to the filtered signal.

This disclosure is directed to, among other things, techniques to decouple the number of bits in a quantizer from the number of bits in the feedback digital-to-analog converter (DAC). A delta-sigma analog-to-digital converter circuit can include a first quantizer to generate an output having a first number of bits and then emulate a second quantizer, such as by using a bit truncation technique, to generate an output having a second number of bits. The feedback DAC can be coupled to receive the second number of bits, where the output of the feedback digital-to-analog converter circuit has the second number of bits. These techniques can reduce the area of the feedback DAC, e.g., 4 or 5 bits, and the techniques can achieve a higher maximum stable amplitude (MSA) because it is effectively a second order loop.

A circuit includes an operational amplifier and a resistor network coupled to an output of the operational amplifier. The resistor network includes a first set of resistors coupled between the output of the operational amplifier and a first node of the resistor network, wherein the resistors of the first set are electrically connected in series with each other, a second set of resistors coupled between the first node and a second node of the resistor network, wherein the resistors of the second set are electrically connected in series with each other and include a first number of resistors, a third set of resistors coupled between the second node and a third node of the resistor network, wherein the third node is coupled to a first voltage, and wherein the resistors of the third set are electrically connected in parallel with each other and include a second number of resistors, and a resistor coupled between the first node and the second node and arranged in parallel with the second set of resistors.

Disclosed herein is a temperature compensated crystal oscillator, TCXO, comprising: a crystal oscillator arrangement configured to generate an output signal of the temperature compensated crystal oscillator; and a temperature sensor arranged to generate a temperature sensor signal, wherein the output signal of the crystal oscillator arrangement is controlled in dependence on the temperature sensor signal; wherein: the temperature sensor comprises a plurality of transistor circuits; each transistor circuit comprises a transistor and a bias circuit; each transistor circuit is arranged to output a temperature signal that is dependent on the temperature of the transistor comprised by the transistor circuit; each bias circuit is configured such that the noise level in each output temperature signal is low; and the plurality of transistor circuits are arranged so that the temperature sensor signal is dependent on each of the plurality of output temperature signals.