In a method in a computer system for recoding a coded intermediate variable into a recoded result variable a product is formed by multiplying an input constant by an input variable to be coded. The coded intermediate variable is formed as a function of the product and a multiplicative inverse is determined on the basis of the input constant. The multiplicative inverse is applied to the coded intermediate variable, so that no uncoded or partially uncoded interim result is produced and/or an error information potentially contained in the coded intermediate variable is still detectable in the interim result.

In a method in a computer system for recoding a coded intermediate variable into a recoded result variable a product is formed by multiplying an input constant by an input variable to be coded. The coded intermediate variable is formed as a function of the product and a multiplicative inverse is determined on the basis of the input constant. The multiplicative inverse is applied to the coded intermediate variable, so that no uncoded or partially uncoded interim result is produced and/or an error information potentially contained in the coded intermediate variable is still detectable in the interim result.

A read is aligned to a reference data set. It is determined whether the read includes any identifier distinction, the determination being performed using the alignment. If so, positional data corresponding to the identifier distinction(s) are defined. Compressed read data is stored in association with a read identifier of the read. The compressed read data includes alignment information (e.g., a start and/or stop position of the alignment). When the read includes an identifier distinction, the compressed read data further includes the positional data and deviation data characterizing the distinction.

A level shifter, a digital-to-analog converter (DAC), and a buffer amplifier, and a source driver and an electronic device including the same are provided. The source driver includes a level shifter configured to receive digital bits and provide a level-shifted output signal; a DAC including a resistor string configured to provide a plurality of gradation voltages formed by an upper limit voltage and a lower limit voltage being received through one end and the other end, and an N-type metal oxide semiconductor (NMOS) switch and a P-type MOS (PMOS) switch configured to be controlled by the level-shifted output signal and output a gradation voltage corresponding to the level-shifted output signal; and an amplifier configured to amplify a signal provided by the digital-to-analog converter, and the lower limit voltage is provided to a body electrode of the NMOS switch.

A level shifter, a digital-to-analog converter (DAC), and a buffer amplifier, and a source driver and an electronic device including the same are provided. The source driver includes a level shifter configured to receive digital bits and provide a level-shifted output signal; a DAC including a resistor string configured to provide a plurality of gradation voltages formed by an upper limit voltage and a lower limit voltage being received through one end and the other end, and an N-type metal oxide semiconductor (NMOS) switch and a P-type MOS (PMOS) switch configured to be controlled by the level-shifted output signal and output a gradation voltage corresponding to the level-shifted output signal; and an amplifier configured to amplify a signal provided by the digital-to-analog converter, and the lower limit voltage is provided to a body electrode of the NMOS switch.

Methods are provided for efficiently encoding and decoding multivariate correlated data sequences for transmission over multiple channels of a network. The methods include transforming data vectors from correlated sources into vectors that comprise substantially independent and correlated components, and generating a common information vector based on the correlated components, and two private information vectors. The methods also include computing the amount of information, such as Wyner's lossy common information, in the common information vector, computing rates that lie on the Gray-Wyner rate region, and choosing compression rates based on the amount of common information. The methods may be applicable, in general, to a wide range of communications and/or storage systems and, particularly, to sensor networks and multi-user virtual environments for gaming and other applications.

A variable output data rate converter circuit preferably meets performance requirements while keeping the circuit complexity low. In some embodiments, the converter circuit may include an oversampling sigma delta modulator circuit to quantize an analog input signal at an oversampled rate, and output an sigma delta modulated signal, a transposed polynomial decimator circuit to decimate the sigma delta modulated signal, and output a first decimated signal, and an integer decimator circuit to decimate the first decimated signal by an integer factor and output a second decimated signal having a desired output data rate. The transposed polynomial decimator circuit has a transposed polynomial filter circuit and a digital phase locked loop circuit, which tracks a ratio between a sampling rate of the first decimated signal and the oversampled rate, and outputs an intersample position parameter to the transposed polynomial filter circuit.

A data compressor includes a zero-value remover, a zero bit mask generator and a non-zero values packer. The zero-value remover receives 2.sup.N bit streams of values and outputs 2.sup.N non-zero-value bit streams having zero values removed from each respective bit stream based on a selected granularity of compression for values contained in the bit streams. The zero bit mask generator receives the 2.sup.N bit streams of values and generates a zero bit mask corresponding to the selected granularity of compression. Each zero bit mask indicates a location of a zero value based on the selected granularity of compression. The non-zero values packer receives the 2.sup.N non-zero-value bit streams and forms at least one first group of packed non-zero values.

A data compressor includes a zero-value remover, a zero bit mask generator and a non-zero values packer. The zero-value remover receives 2.sup.N bit streams of values and outputs 2.sup.N non-zero-value bit streams having zero values removed from each respective bit stream based on a selected granularity of compression for values contained in the bit streams. The zero bit mask generator receives the 2.sup.N bit streams of values and generates a zero bit mask corresponding to the selected granularity of compression. Each zero bit mask indicates a location of a zero value based on the selected granularity of compression. The non-zero values packer receives the 2.sup.N non-zero-value bit streams and forms at least one first group of packed non-zero values.

Systems and methods are disclosed for improving data channel design by applying transform domain analytics to more reliably extract user data from a signal. In certain embodiments, an apparatus may comprise a channel circuit configured to receive an analog signal at an input of the channel circuit, and sample the analog signal to obtain a set of signal samples. The channel circuit may further apply a filter configured to perform transform domain analysis to the set of signal samples to generate a first subset of samples, the first subset including fewer transitions and having a higher signal to noise ratio (SNR) than the set of signal samples. The channel circuit may detect first bit transform domain representation values from the first subset, and determine channel bit values encoded in the analog signal based on the set of signal samples and using the first bit transform domain representation values detected from the first subset as side information.