An apparatus comprises a sigma-delta analog-to-digital converter (ADC) circuit including a serial data input, a serial data output, a serial clock input to receive a serial clock signal, and a master clock input to receive a master clock signal; a digital isolator circuit including outputs coupled to the serial clock input and serial data input of the sigma-delta ADC circuit, and an input coupled to the serial data output of the sigma-delta ADC circuit; an oscillator circuit unconnected to the digital isolator circuit and configured to generate the master clock signal asynchronous to the serial clock input signal; and wherein the sigma-delta ADC circuit generates an ADC sampling clock using the master clock.

A layered coding method based on high order modulation comprising: S1: inputting serial data flow from a serial data input end into a serial-to-parallel converter; S2: inputting the data flow treated by the serial-to-parallel converter into the a multi-layer coder; S3: correlating the coders at individual layers with each other and transmitting information based on high order modulation; S4: inputting the data flow treated by the coders at individual layers into a modulator for modulation mapping processing; S5: outputting the data flow from the output end of the modulator. By means of correlating coders at layers with each other, the coder at each layer can code the data of its own layer while transmitting the data to the coder at a higher layer for protection, until reaching the coder at the highest layer, improving the coding rate, error correcting ability and data processing performance in a multi-layer coder

A layered coding method based on high order modulation comprising: S1: inputting serial data flow from a serial data input end into a serial-to-parallel converter; S2: inputting the data flow treated by the serial-to-parallel converter into the a multi-layer coder; S3: correlating the coders at individual layers with each other and transmitting information based on high order modulation; S4: inputting the data flow treated by the coders at individual layers into a modulator for modulation mapping processing; S5: outputting the data flow from the output end of the modulator. By means of correlating coders at layers with each other, the coder at each layer can code the data of its own layer while transmitting the data to the coder at a higher layer for protection, until reaching the coder at the highest layer, improving the coding rate, error correcting ability and data processing performance in a multi-layer coder

A system and method for efficiently transferring data between devices. In various embodiments, a host computing device receives parallel data, encodes the parallel data as a count of pulses as serial data, and conveys the serial data to a peripheral device. The peripheral device decodes the received serial data to determine the parallel data, which is sent to processing logic. The devices send the encoded pluses on a bidirectional line, so the pulses are capable of being sent in both directions. The devices send the encoded pulses on the bidirectional line using a non-zero base voltage level. The devices are capable of using a voltage headroom when conveying encoded pulses between one another. Therefore, a full voltage swing between a ground reference voltage level and a power supply voltage level is not used when conveying the encoded pulses, which reduces power consumption.

Embodiments provide one write operation circuit, which includes: a serial-to-parallel conversion circuit that performs serial-to-parallel conversion on a first DBI data of a DBI port to generate a second DBI data for transfer by a DBI signal line, and that generates an input data of a data buffer module depending on the second DBI data; a data buffer module that determines whether to flip a global bus depending on the input data of the data buffer module; the DBI decoding module that decodes a global bus data according to the second DBI data, and writes the decoded data into a memory bank, where decoding includes determining whether to flip the global bus data; and a precharge module that is coupled to a precharge signal line and that sets the initial state of the global bus to high.

Embodiments provide one write operation circuit, which includes: a serial-to-parallel conversion circuit that performs serial-to-parallel conversion on a first DBI data of a DBI port to generate a second DBI data for transfer by a DBI signal line, and that generates an input data of a data buffer module depending on the second DBI data; a data buffer module that determines whether to flip a global bus depending on the input data of the data buffer module; the DBI decoding module that decodes a global bus data according to the second DBI data, and writes the decoded data into a memory bank, where decoding includes determining whether to flip the global bus data; and a precharge module that is coupled to a precharge signal line and that sets the initial state of the global bus to high.

Described are apparatus and methods for low power clock generation in multi-channel high speed devices. In implementations, a multi-channel data processing device includes a low frequency clock generation and distribution circuit configured to generate and distribute a 1/N sampling frequency (F.sub.S)(F.sub.S/N) clock, wherein N is larger or equal to 8, and multiple data processing channels connected to the low frequency generation and distribution circuit. Each data processing channel including input ports associated with different operating frequency clocks, and a channel local clock generation circuit comprising multipliers associated with some of the input ports, each multiplier configured to multiply the F.sub.S/N frequency clock to locally generate an operating frequency clock associated with an input port of the input ports.

An illustrative embodiment of a packaged integrated circuit includes: an integrated circuit chip having a SerDes signal pad; and a package substrate having a core via and an arrangement of micro-vias connecting the SerDes signal pad to an external contact for solder ball connection to a PCB trace. The core via has a first parasitic capacitance, the solder ball connection is associated with a second parasitic capacitance, and the arrangement of micro-vias provides a pi-network inductance that improves connection impedance matching. An illustrative method embodiment includes: obtaining an expected impedance of the PCB trace; determining parasitic capacitances of a core via and a solder ball connection to the PCB trace; minimizing the core via capacitance; calculating a pi-network inductance that improves impedance matching with the PCB trace; and adjusting a micro-via arrangement between the core via and the solder ball connection to provide the pi-network inductance.

An illustrative embodiment of a packaged integrated circuit includes: an integrated circuit chip having a SerDes signal pad; and a package substrate having a core via and an arrangement of micro-vias connecting the SerDes signal pad to an external contact for solder ball connection to a PCB trace. The core via has a first parasitic capacitance, the solder ball connection is associated with a second parasitic capacitance, and the arrangement of micro-vias provides a pi-network inductance that improves connection impedance matching. An illustrative method embodiment includes: obtaining an expected impedance of the PCB trace; determining parasitic capacitances of a core via and a solder ball connection to the PCB trace; minimizing the core via capacitance; calculating a pi-network inductance that improves impedance matching with the PCB trace; and adjusting a micro-via arrangement between the core via and the solder ball connection to provide the pi-network inductance.

The invention relates to a method for determining a time of a flank in a signal, wherein the method comprises a step of reading the signal and has a master clock rate for operating a digital evaluation unit for evaluating the time of the flank. The method also comprises a step of forming a data word representing the signal, using a deserializer of a SERDES cell, wherein the data word has a plurality of bits, and wherein a sampling clock rate is applied to the SERDES cell for sampling the signal, which sampling clock rate is higher than the master clock rate, wherein one flank or two flanks of the sampling clock rate are used for sampling the signal. Finally, the method comprises a step of determining the time of the flank in the signal using the data word and the master clock rate in the evaluation unit.