A system and method for efficiently transferring data between devices. In various embodiments, a host computing device receives parallel data, encodes the parallel data as a count of pulses as serial data, and conveys the serial data to a peripheral device. The peripheral device decodes the received serial data to determine the parallel data, which is sent to processing logic. The devices send the encoded pluses on a bidirectional line, so the pulses are capable of being sent in both directions. The devices send the encoded pulses on the bidirectional line using a non-zero base voltage level. The devices are capable of using a voltage headroom when conveying encoded pulses between one another. Therefore, a full voltage swing between a ground reference voltage level and a power supply voltage level is not used when conveying the encoded pulses, which reduces power consumption.

A system and method for efficiently transferring data between devices. In various embodiments, a host computing device receives parallel data, encodes the parallel data as a count of pulses as serial data, and conveys the serial data to a peripheral device. The peripheral device decodes the received serial data to determine the parallel data, which is sent to processing logic. The devices send the encoded pluses on a bidirectional line, so the pulses are capable of being sent in both directions. The devices send the encoded pulses on the bidirectional line using a non-zero base voltage level. The devices are capable of using a voltage headroom when conveying encoded pulses between one another. Therefore, a full voltage swing between a ground reference voltage level and a power supply voltage level is not used when conveying the encoded pulses, which reduces power consumption.

A parallel-to-serial conversion circuit includes: parallel branches, each including first input end, second input end, control ends and output end, where first input end is configured to receive high level signal, second input end is configured to receive low level signal, control ends are connected to selection unit and output end is connected to serial wire, and selection unit is configured to receive selection signal and at least two branch signals and configured to select, based on selection signal, one branch signal and transmit it to parallel branch; serial wire configured to organize signals output by parallel branches into serial signal; and drive units connected in parallel with each other and connected to serial wire for enhancing drive capability of serial wire, output ends of drive units being connected with each other and configured to output serial signal, and each drive unit being disposed adjacent to a respective parallel branch.

A parallel-to-serial conversion circuit includes: parallel branches, each including first input end, second input end, control ends and output end, where first input end is configured to receive high level signal, second input end is configured to receive low level signal, control ends are connected to selection unit and output end is connected to serial wire, and selection unit is configured to receive selection signal and at least two branch signals and configured to select, based on selection signal, one branch signal and transmit it to parallel branch; serial wire configured to organize signals output by parallel branches into serial signal; and drive units connected in parallel with each other and connected to serial wire for enhancing drive capability of serial wire, output ends of drive units being connected with each other and configured to output serial signal, and each drive unit being disposed adjacent to a respective parallel branch.

Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.

Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.

Systems and methods are provided for timing signals, measuring latency, and/or timestamping. Some of the systems described herein can measure latency in a network device, and can include a signal generator, a sampler, a pulse detector, a timer, and a connector. The signal generator can define a signal profile. The sampler can sample the signal profile at a frequency of at least 4 GHz to generate a plurality of bits, each bit corresponding to a value of the signal profile during the sampling. The pulse detector can detect a change in the signal profile by detecting at least one change in the plurality of bits. The timer can time the change in value in the plurality of bits to provide at least one detection time measurement. The connector can electronically link the signal generator and the sampler to the network device to provide an external network path for transmitting a signal from the signal generator to the sampler via the network device.

Aspects of the disclosure provide a semiconductor device. For example, the semiconductor device can include a first deserializer, a second deserializer, and a write data converter coupled to the first deserializer and the second deserializer. The first deserializer can be configured to convert serial data to parallel data based on a set of write clock signals, thus the parallel data has a first timing alignment with regard to the set of write clock signals. The second deserializer can be configured to generate a mask pattern based on the set of write clock signals, thus the mask pattern has a second timing alignment with regard to the set of write clock signals. The write data converter can be configured to generate valid data based on the parallel data and the mask pattern.

A transmitter circuit that receives parallel signals and outputs a serial signal in response to the parallel signals may include; a clock generator generating first clock signals having different respective phases, a multiplexer including selection circuits respectively configured to selectively provide at least two of the parallel signals to an output node in response to at least two of the first clock signals, and an output driver generating the serial signal by amplifying a signal at the output node.

A transmitter circuit includes a clock generator configured to generate a plurality of clock signals having different phases, and a plurality of selection circuits configured to receive a plurality of parallel data signals and output a serial data signal on an output node based on the plurality of clock signals and the received plurality of parallel data signals. Each of the plurality of selection circuits includes a data multiplexer configured to generate a plurality of data selection signals based on the received one of the plurality of parallel data signals and the plurality of clock signals; a control signal generator configured to generate first and second control signals based on the plurality of data selection signals; and an output driver connected to the output node, and configured to precharge the output node based on the first control signal or discharge the output node based on the second control signal.