The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.

A buffer includes an amplification circuit, an amplification current generation circuit, and a latch. The amplification circuit may change voltage levels of a first output node and a second output node based on a clock signal and a pair of input signals. The amplification current generation circuit may provide currents having different magnitudes to the first and second output nodes during a first operation period, and may provide currents having the same magnitude to the first and second output nodes during a second operation period. The latch circuit may latch the voltage levels of the first output node and the second output node based on the clock signal.

A buffer includes an amplification circuit, an amplification current generation circuit, and a latch. The amplification circuit may change voltage levels of a first output node and a second output node based on a clock signal and a pair of input signals. The amplification current generation circuit may provide currents having different magnitudes to the first and second output nodes during a first operation period, and may provide currents having the same magnitude to the first and second output nodes during a second operation period. The latch circuit may latch the voltage levels of the first output node and the second output node based on the clock signal.

A frequency divider circuit includes: a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divided clock signal; a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal; a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit.

A serializer may be provided. The serializer may include a first data output circuit and a second data output circuit. The first data output circuit may provide first data to an output node in synchronization with a first phase clock and a second phase clock. The second data output circuit may provide second data to the output node in synchronization with the second phase clock and a third phase clock. The first data output circuit may perform a precharge operation or an emphasis operation for the second data output circuit, in synchronization with a third phase clock.

An analog to digital converter is provided. The analog to digital converter includes: an arithmetic operator combining an analog input signal with a feedback signal; a loop filter filtering an output signal of the arithmetic operator; a quantizer quantizing an output signal of the loop filter to output a digital signal; and a feedback converting the digital signal to output a feedback signal, in which the quantizer includes: a plurality of VCOs each receiving a positive output signal and a negative output signal of the loop filter and outputting VCO signals; a plurality of samplers receiving the VCO signals output from the plurality of VCOs, respectively and outputting sampled signals; and a phase detector detecting a phase difference in the sampled signals output from the plurality of samplers, respectively, to detect a phase difference in two VCO signals output from the plurality of VCOs, respectively.

There is disclosed herein multiplexer circuitry. In particular, there is disclosed a latch circuit for use as a multiplexer to multiplex information carried by respective pairs of input information signals onto an output information signal, each pair of input information signals comprising a first input information signal and a second input information signal, and each pair of input information signals carrying information values based on signal values of those input information signals and interleaved with information values carried by the other pair or pairs of input information signals.

An OFDM modulator including a predistortion module configured to receive the N consecutive data carriers and configured to compensate for distortion subsequently introduced by a polyphase filter bank connectable to the output of the OFDM modulator, a transformation module configured to apply a discrete inverse Fourier transform of constant size N.sub.IDFT independently of the numbering and transmission band used by the OFDM transmitter including the OFDM modulator, a filling module, the input of which is connected to the output of the predistortion module, and the output of which is connected to the input of the transformation module, and configured to insert (N.sub.IDFT−N.sub.c) null carriers in succession to the N.sub.c consecutive data carriers independently of the parity of the index i associated with the OFDM modulator.

An OFDM modulator including a predistortion module configured to receive the N consecutive data carriers and configured to compensate for distortion subsequently introduced by a polyphase filter bank connectable to the output of the OFDM modulator, a transformation module configured to apply a discrete inverse Fourier transform of constant size N.sub.IDFT independently of the numbering and transmission band used by the OFDM transmitter including the OFDM modulator, a filling module, the input of which is connected to the output of the predistortion module, and the output of which is connected to the input of the transformation module, and configured to insert (N.sub.IDFT−N.sub.c) null carriers in succession to the N.sub.c consecutive data carriers independently of the parity of the index i associated with the OFDM modulator.

A data transmitter includes: a plurality of parallel driver slices, a first slice of the plurality of parallel driver slices having a first signal generator circuit with a first transistor coupled to a data signal and in series with a second transistor coupled to a first bias signal; and a first bias circuit including a third transistor and a fourth transistor in series with a first current source, the first bias circuit further including a first operational amplifier (op amp) having a first input coupled to a first reference voltage and a second input coupled between the fourth transistor and the first current source, an output of the first op amp configured to provide the first bias signal to the second transistor and to the third transistor.