A decompression apparatus is provided. The decompression apparatus includes a memory configured to store compressed data decompressed and used in neural network processing of an artificial intelligence model, a decoder configured to include a plurality of logic circuits related to a compression method of the compressed data, decompress the compressed data through the plurality of logic circuits based on an input of the compressed data, and output the decompressed data, and a processor configured to obtain data of a neural network processible form from the data output from the decoder.

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to perform by group-wise interleaving a plurality of bit groups configuring the parity bits based on a group-wise interleaving pattern comprising a first pattern and a second pattern; a puncturer configured to puncture some of the parity-permutated parity bits; and an additional parity generator configured to select at least some of the punctured parity bits to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern.

Techniques to facilitate compression of depth data and real-time reconstruction of high-quality light fields. A parameter space of values for a line, pairs of endpoints on different sides of the line, and a palette index for each pixel of a pixel tile of a depth image is sampled. Values for the line, the pairs of endpoints, and the palette index that minimize an error are determined and stored.

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme.

A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each imade up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.

According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller manages a plurality of namespaces for storing a plurality of kinds of data having different update frequencies. The controller encodes write data by using first coding for reducing wear of a memory cell to generate first encoded data, and generates second encoded data to be written to the nonvolatile memory by adding an error correction code to the first encoded data. The controller changes the ratio between the first encoded data and the error correction code based on the namespace to which the write data is to be written.

Systems, devices, and methods for encoding information bits for storage, including encoding information bits and balance bits to obtain a first bit chunk of a first arrangement; permuting the first bit chunk to obtain a second bit chunk of a second arrangement; encoding the second bit chunk to obtain a third bit chunk of the second arrangement; permuting a first portion of the third bit chunk to obtain a fourth bit chunk of the first arrangement, and encoding the fourth bit chunk to obtain a fifth bit chunk of the first arrangement; permuting a second portion of the third bit chunk, and adjusting the balance bits based on the fifth bit chunk and the permutated second portion of the third bit chunk; adjusting the first arrangement based on the adjusted balance bits, and obtaining a codeword based on the adjusted first arrangement; and transmitting the codeword to a storage device.

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to group-wise interleave a plurality of bit groups including the parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups at predetermined positions in the bit groups before the group-wise interleaving are positioned serially after the group-wise interleaving and a remainder of the bit groups before the group-wise interleaving are positioned without an order after the group-wise interleaving so that the puncturer selects parity bits included in the some of the bit groups sequentially and selects parity bits included in the remainder of the bit groups without an order.

A decoding method, a memory storage device, and a memory control circuit unit are provided. The decoding method includes: reading a codeword from a memory module and estimating error level information of the codeword; inputting the codeword and the error level information to an error checking and correcting circuit through a first message channel and a second message channel respectively; determining whether the error level information meets a default condition; if yes, inputting the codeword to a first decoding engine of the error checking and correcting circuit for decoding; otherwise, inputting the codeword to a second decoding engine of the error checking and correcting circuit for decoding, wherein a power consumption of the first decoding engine is lower than that of the second decoding engine, and a decoding success rate of the first decoding engine is lower than that of the second decoding engine. Therefore, an operating flexibility for decoding may be improved.