A method and apparatus for determining the sector size and concomitant host metadata size to determine the difference between total size of the data block to be stored, and using the difference for parity data. This allows an increase in parity bits available for smaller sector sizes and/or data with smaller host metadata sizes. Because the amount of space available for additional parity bits is known, data with lower numbers of parity bits may be assigned to higher quality portions a memory array written with longer programming trim times, and/or written to memory dies with good redundant columns, further increasing performance and reliability.

Systems and methods are provided for decoding data read from non-volatile storage devices. A method that may include decoding a first codeword read from a storage location of a non-volatile storage device using a first decoder without soft information, determining that the first decoder has failed to decode the first codeword, decoding the first codeword using a second decoder without soft information, determining that the second decoder has succeeded in decoding the first codeword, generating soft information associated with the storage location using decoding information generated by the second decoder and decoding a subsequent codeword from the storage location using the soft information associated with the storage location. The second decoder may be more powerful than the first decoder.

A processing system is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit comprising an error detection circuit configured to receive data bits and respective Error Correction Code, ECC, bits, wherein the data bits correspond to the first, second or third data. The safety monitor circuit calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit receives the error signal from the safety monitor circuits. For example the safety monitor circuit comprises a test circuit configured to provide modified data bits and/or modified ECC bits to the error detection circuit as a function of connectivity test control signals, whereby the error detection circuit asserts the error signal as a function of the connectivity test control signals. The processing system comprises also a connectivity test control circuit comprising control registers programmable via the microprocessor, wherein the connectivity test control signals are generated as a function of the content of the control registers.

A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller to store the counted values in each of the plurality of memory cell rows as count data, determines a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed more than a predetermined reference number of times, based on the counted values, and performs an internal read-update-write operation. The refresh control circuit receives the hammer address and to perform a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

A quantum error correcting code with dynamically generated logical qubits is provided. When viewed as a subsystem code, the code has no logical qubits. Nevertheless, the measurement patterns generate logical qubits, allowing the code to act as a fault-tolerant quantum memory. Each measurement can be a two-qubit Pauli measurement.

A system and method for polar code coding with information bits placed in particular bit indexes are disclosed herein. In one embodiment, a method for channel coding includes: associating, by a polar code encoder, a first bit sequence with first bit indexes of a polar code input; associating, by the polar code encoder, a second bit sequence with second bit indexes, wherein the first bit indexes have a higher reliability than the second bit indexes; and encoding, by the polar code encoder, both the first bit sequence and the second bit sequence using a generator matrix to generate encoded bits.

A data encoding device suitable for encoding a plurality of LDPC codes is disclosed including an input interface and an output interface, and a first circuit for encoding quasi-cyclic LDPC code, connected at an input to the input interface and at an output to the input of a first multiplexer circuit, a second circuit for encoding quasi-cyclic LDPC code, connected at an input to the input interface and at an output to the input of the first multiplexer circuit, a third circuit for encoding quasi-cyclic LDPC code, connected at an input to the output of the first multiplexer circuit and at an output to the input of a second multiplexer circuit.

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Systems, methods, and instrumentalities are described herein for supporting CBG-based retransmission with variable CBG size using variable length HARQ-ACK. A WTRU may receive a configuration to use a first table. The first table may be associated with a maximum number of code block groups per transport block (maxCBG/TB). The WTRU may determine a number of HARQ-ACK bits to send for code blocks. The determination may depend on whether an indication is received to switch from the first table to a second table. On a condition that the indication to switch from the first table to the second table is received, the WTRU may send a number of HARQ-ACK bits that is equal to two times the maxCBG/TB. The WTRU may receive a retransmission of a number of code blocks, wherein a code block group size depends on a sent number of HARQ-ACK bits.

A particular overall architecture for transmission over a bonded channel system consisting of two interconnected MoCA (Multimedia over Coax Alliance) 2.0 SoCs (Systems on a Chip) and a method and apparatus for the case of a “bonded” channel network. With a bonded channel network, the data is divided into two segments, the first of which is transported over a primary channel and the second of which is transported over a secondary channel.