According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.

Aspects of the disclosure relate to wireless communication devices configured to encode information blocks to produce code blocks and interleave the code blocks utilizing an interleaver including a plurality of rows and a plurality of columns, where the number of columns of the interleaver varies between the rows. In some examples, the interleaver includes a right isosceles triangle-shaped matrix of rows and columns. In other examples, the interleaver includes a trapezoid-shaped matrix of rows and columns.

A method and associated apparatus is disclosed for processing data by means of an error code, wherein the error code has an H-matrix with n columns and m rows, wherein the columns of the H-matrix are different, wherein component-by-component XOR sums of adjacent columns of the H-matrix are different from one another and from all columns of the H-matrix and wherein component-by-component XOR sums of nonadjacent columns of the H-matrix are different from all columns of the H-matrix and from all component-by-component XOR sums of adjacent columns of the H-matrix.

A method and an apparatus for encoding a polar code concatenated with a cyclic redundancy check (CRC), where M bits are selected from K bits in the sequence to perform CRC encoding. The M bits are determined based on reliability of K polarized subchannels on which the K bits are placed and/or row weights of K rows, in a first matrix, corresponding to the K polarized subchannels on which the K bits are placed. The first matrix is an encoding matrix of polar encoding. Polar encoding is performed on the K bits and obtained CRC check bits. An encoded codeword is output.

A method for Bose-Chaudhuri-Hocquenghem (BCH) soft error decoding includes receiving a codeword x, wherein the received codeword x has τ=t+r errors for some r≥1; computing a minimal monotone basis {λ.sub.i(x)}.sub.1≤i≤r+1.Math.F[x] of an affine space V={λ(x)∈F[x]:λ(x).Math.S(x)=λ′(x) (mod x.sup.2t), λ(0)=1, deg(λ(x)≤t+r}, wherein λ(x) is an error locator polynomial and S(x) is a syndrome; computing a matrix A≡(λ.sub.j(β.sub.i)).sub.i∈[w],j∈[r+1], wherein W={β.sub.1, . . . , β.sub.w} is a set of weak bits in x; constructing a submatrix of r+1 rows from sub matrices of r+1 rows of the subsets of A such that the last column is a linear combination of the other columns; forming a candidate error locating polynomial using coefficients of the minimal monotone basis that result from the constructed submatrix; performing a fast Chien search to verify the candidate error locating polynomial; and flipping channel hard decision at error locations found in the candidate error locating polynomial.

Methods and systems for improving the robustness of wireless communications. The methods and systems provided transmit data packets over one or more isochronous stream and transmit one or more supplemental data packets over the same time intervals. The one or more supplemental data packets are used to recreate and/or enhance at least a portion of one or more data packets of the plurality of data packets that have already been sent. Alternatively, the one or more supplemental data packets are used to create and/or enhance at least a portion of one or more data packets of the plurality of data packets that will be received during the next isochronous intervals. The methods and system described herein allow for increased robustness by allowing for better retransmission with correctly received packets.

A quantum computing system for converting Pauli errors of one or more qubits to erasure errors in a photonic quantum computing architecture. Two or more photonic qubits may be input to a quantum computing system, where at least one first qubit of the two or more qubits has experienced a Pauli error. A sequence of linear optical circuitry operations may be performed on the two or more qubits to generate two or more modified qubits, wherein the sequence of operations transforms one or more of the first qubits from a logical subspace of a Fock space to an erasure subspace of the Fock space. A cluster state for universal quantum computing may be generated from the two or more modified qubits using probabilistic entangling gates. A quantum computational algorithm may be performed using the quantum cluster state generated from the two or more modified qubits.

A signal receiving method include: demodulating a signal received from a transmitting apparatus to generate values based on 1024-quadrature amplitude modulation (QAM); splitting the values into a plurality of groups; deinterleaving the plurality of groups based on a preset interleaving order; and decoding values of the deinterleaved plurality of groups based on a low density parity check (LDPC) code, a code rate of the LDPC code being 6/15 and a code length of the LDPC code being 64800, wherein the plurality of groups are deinterleaved based on a predetermined equation.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.