H03M13/00

Systems and methods for transition encoding with protected key

A method for encoding may include receiving, at an encoder, a series of data bits, performing, at the encoder, first transition encoding on the data bits to generate an encoded series of data bits based on a key, performing, at the encoder, protection encoding on the key to generate key protection data, performing, at the encoder, second transition encoding on the key protection data to generate encoded key protection data, and transmitting an encoded series of transmission bits to a receiver, the encoded series of transmission bits including the encoded series of data bits and the encoded key protection data.

Method for decoding polar codes and apparatus thereof

A method and an apparatus for decoding polar codes, the method comprising: determining a starting level for processing an overflow according to a number of encoded bits of a received polar encoded codeword, an input bit-width, and an internal bit-width of a decoder; multiplying an output Log-Likelihood Ratio (LLR) value and two input LLR values of the G function by a first coefficient and a second coefficient respectively; and finally, the LLR values corresponding to the received codeword are decoded to obtain decoded bits.

LOW-LATENCY SEGMENTED QUASI-CYCLIC LOW-DENSITY PARITY-CHECK (QC-LDPC) DECODER

Systems and methods which provide parallel processing of multiple message bundles for a codeword undergoing a decoding process are described. Embodiments provide low-latency segmented quasi-cyclic low-density parity-check (QC-LDPC) decoder configurations in which decoding process tasks are allocated to different segments of the low-latency segmented QC-LDPC decoder for processing multiple bundles of messages in parallel. A segmented shifter of a low-latency segmented QC-LDPC decoder implementation may be configured to process multiple bundles of a plurality of edge paths in parallel. Multiple bundles of messages of a same check node cluster (CNC) are processed in parallel. Additionally, multiple bundles of messages of a plurality of CNCs are processed in parallel.

Increased data reliability

A method for adjustable error correction in a storage cluster is provided. The method includes determining health of a non-volatile memory of a non-volatile solid-state storage unit of each of a plurality of storage nodes in a storage cluster on a basis of per flash package, per flash die, per flash plane, per flash block, or per flash page. The determining is performed by the storage cluster. The plurality of storage nodes is housed within a chassis that couples the storage nodes as the storage cluster. The method includes adjusting erasure coding across the plurality of storage nodes based on the health of the non-volatile memory and distributing user data throughout the plurality of storage nodes through the erasure coding. The user data is accessible via the erasure coding from a remainder of the plurality of storage nodes if any of the plurality of storage nodes are unreachable.

Transformation of data to non-binary data for storage in non-volatile memories

A data storage system and method are provided for storing data in non-volatile memory devices. Binary data is received for storage in a non-volatile memory device. The binary data is converted into non-binary data comprising base-X values, where X is an integer greater than two. The non-binary data is encoded to generate a codeword and the codeword is written to a wordline of the non-volatile memory device.

METHOD OF PERFORMING A DISTRIBUTED TASK OVER A NETWORK
20220416944 · 2022-12-29 ·

An aspect of the invention provides a method of performing a distributed task over a network comprising a plurality of nodes. The method comprises: a plurality of network nodes observing (300) data; applying a first linear code function to the data observed by at least one network node of the plurality of network nodes to obtain (302) at least one function output; applying errors (304) to the at least one function output; a query node selected from the network nodes performing (308) a mixing procedure to aggregate node observations to obtain a first set of aggregated values until a stopping criteria (306) is satisfied; applying (312) a second linear code function to the set of aggregated values to obtain a second set of aggregated values returned to their observed domain; and the query node outputting (314) the second set of aggregated values.

Integrated circuit for reception apparatus

Disclosed are an encoder, a transmission device, and an encoding method with which the transmission amount is reduced and a deterioration in transmission efficiency is suppressed while improving reception quality when QC-LDPC or a like block encoding is used. A puncture pattern setting unit (620) searches for a puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of a sub block matrix that forms a check matrix (H) of a QC-LDPC code, and a puncture unit (data reduction unit) (630) switches the puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of the sub block matrix that forms the check matrix of the QC-LDPC code.

Transmitter, receiver, and signal processing method thereof

A transmitter and receiver of a broadcasting signal and a method of processing the broadcasting signal are provided. The transmitter includes: a segmenter configured to segment an L1 signaling of a frame into a plurality of segmented L1 signalings such that each of the segmented L1 signalings has bits a number of which is equal to or smaller than a predetermined number; and an encoder configured to perform a Bose, Chaudhuri, Hocquenghem (BCH) and a low density parity check (LDPC) encoding, or the LDPC encoding without the BCH encoding, with respect to the segmented L1 signalings.

Method for encoding information in communication network

Embodiments of the application provide a method for rate matching in a wireless communication network. A device obtains K information bits and a target code length M of a polar code, determines, according to a minimum value of a set of values, a mother code length N.sub.1, polar encodes the K information bits to obtain an encoded sequence of N.sub.1 bits, obtains a target sequence of M bits from the N.sub.1 bit encoded sequence, and outputs the M-bit target sequence. When the mother code length N.sub.1 is larger than the target code length M, (N.sub.1−M) bits of the encoded sequence are punctured or shortened from the N.sub.1 bit encoded sequence.

Memory system

In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.