A network device includes one or more ports for connecting to a communication network, packet processing circuitry and clock circuitry. The packet processing circuitry is configured to communicate packets over the communication network via the ports. The clock circuitry includes a hardware clock configured to indicate a network time used for synchronizing network devices in the communication network, and a built-in accuracy test circuit configured to check an accuracy of the hardware clock.

An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.

Signal conditioning circuitry includes logic circuitry, a low-pass filter, and comparator circuitry. The logic circuitry is configured to compare a data unit with a preceding data unit, from a sequence of data units, and provide a logic output signal. The low-pass filter is coupled to the logic circuitry, and the low-pass filter is configured to provide a data transition density measurement for the sequence of data units based on the logic output signal. The comparator circuitry is coupled to the low-pass filter, and the comparator circuitry is configured to compare the data transition density measurement to a threshold and, based on the comparison to the threshold, indicate a disruptive pattern in the sequence of data units.

Systems and methods for operating a quantum network system. The methods comprise, by a network node: generating optical clock pulses and photons using the optical clock pulses; generating a combined signal by combining the optical clock pulses with at least some of the photons such that a consistent temporal offset exits between the optical clock pulses and the first photons and/or a wave function of each photon at least partially overlaps an envelope of a respective one of the optical clock pulses; and transmitting the combined signal over a first quantum channel in which the optical clock pulses co-propagate with the photons.

A communication chip includes an input port, a gain circuit, a correction circuit having a phase-locked loop (PLL) circuit and a return terminal, a post-processing circuit, and a switching circuit. The gain circuit includes an input terminal and a quadrature modulation circuit that operates according to a reference clock. The gain circuit gains a signal from the input terminal according to a bias voltage and outputs a gained signal. The PLL circuit generates a correction signal through synchronization according to the reference clock. The post-processing circuit obtains an input signal strength according to a correction table and a signal from a receiving terminal of the post-processing circuit. The switching circuit couples the correction signal to the input terminal and the gained signal to the return terminal in test mode and couples the input port to the input terminal and the gained signal to the receiving terminal in an operating mode.

An optical transmission device includes: a first receiver circuit, a second receiver circuit, a switch circuit, a terminator circuit, a packet buffer, a clock generator, and a signal generator. The first receiver circuit converts an optical signal received via a first route into a first electric signal. The second receiver circuit converts an optical signal received via a second route into a second electric signal. The switch circuit selects the first electric signal or the second electric signal. The terminator circuit extracts a packet from an electric signal selected by the switch circuit. The packet buffer stores the packet extracted by the terminator circuit. The clock generator generates a clock signal. The signal generator generates a continuous signal that includes the packet stored in the packet buffer by using the clock signal.

A method of frequency search and error correction of clock and data recovery circuit, comprising: initializing a frequency search algorithm parameter; processing a frequency error parameter UP/DN signals according to the set algorithm parameter and starting the frequency search, in which, the algorithm accordingly counts the UP/DN signals. When a phase error signal transition occurs, a transition parameter JUMP is accumulated by 1, and an accumulation parameter SUM is obtained and is further judged that whether a frequency search result is to be output. Number of repeating times of verification and threshold parameters are set, accordingly a reset DCRL value is obtained to verifies a frequency locking result and outputs the result. The present invention improves accuracy of UP/DN pulse counting, increases stability and reliability of the frequency locking, avoids a false locking in the frequency locking, and prevents an excessive locking time in the frequency locking, overcomes error judgment of the frequency search caused by a random jitter, and correctly completes the frequency search and locking, avoids failure of the CDR caused by an error frequency locking.

A device includes a transmitter to transmit serialized data within a differential direct-current (DC) signal over a differential output line, a multiplexer circuit coupled to the transmitter, and a calibration circuit coupled between the differential output line, a multi-phase clock, and the multiplexer circuit. The multiplexer circuit is to select the serialized data from ones of multiple input lines according to a multi-phase clock and pass the selected serialized data to the transmitter. The serialized data includes a calibration bit pattern. The calibration circuit is to capture and digitize the differential DC signal into a digital stream, measure an error value from the digital stream that is associated with distortion based on the calibration bit pattern, convert the error value into a gradient value, and correct one or more phases of the multi-phase clock to compensate for the distortion based on the gradient value.

An eye opening monitor device and an operation method thereof are provided. The eye opening monitor device includes a phase interpolator, a first sampling circuit, a second sampling circuit, and a clock centering circuit. The first sampling circuit samples a data signal according to a data clock to generate first sampled data. The second sampling circuit samples the data signal according to a phase interpolation clock to generate second sampled data. The phase interpolator changes a phase of the phase interpolation clock according to a phase interpolation code. The clock centering circuit counts multiple comparison results of the first sampled data and the second sampled data in multiple clock cycles to obtain an error count value for any one of different phase interpolation codes. The clock centering circuit determines the phase interpolation code provided to the phase interpolator based on the error count values corresponding to different phase interpolation codes.

A method and an apparatus for clocking data processing modules, with different average clock frequencies and for transferring data between the modules are provided. The apparatus includes a device for providing a common clock signal to the modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. The clock pulses are applied to the modules between which the data is to be transferred at times consistent with the data transfer.