A short range radio communication device and a method of controlling a short range radio communication device may include a processing circuit configured to: determine a time offset between an initial starting point of operation of a transceiver in accordance with a first frequency hopping sequence and a shifted starting point of operation of the transceiver in accordance with the first frequency hopping sequence so that a first segment of a frequency range is exclusive of a second segment of the frequency range; and control at least one of a controller and a clock circuit to operate the transceiver in accordance with the first frequency hopping sequence at the shifted starting point.

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

A technique is provided for transmitting client data included in a client signal via an optical transmission path of an optical transport network. The optical transport network uses transport frames include a transport frame period for transmitting client data. The method includes receiving multiple client entities comprising multiple client data bits; determining the number of client data entities received during a transport frame period to establish a mean number of client data entities to be included in a transport frame, the mean number of client data entities corresponding to a mean number of client data bits; mapping multiple client data entities into the transport frame wherein mapping comprises alternately adding and subtracting an amount of client data bits to/from the mean number of client data bits for at least two consecutive transport frames; and transmitting the transport frames comprising the client data via the optical transport network.

A polar transmitter provided for transmitting a phase/frequency modulated and amplitude modulated transmit signal and a method for generating a transmit signal using a polar transmitter are described. An example polar transmitter comprises a phase locked loop for generating a phase/frequency modulated precursor of the transmit signal. The phase locked loop comprises at its input a phase error detection unit for detecting a phase error of the precursor fed back from the output of the phase locked loop to the phase error detection unit as a feedback signal. The polar transmitter comprises a digital amplitude modulator for amplitude modulation of the precursor, resulting in the transmit signal. The digital amplitude modulator is arranged within the phase locked loop for amplitude modulation of the precursor before being output by the PLL. The phase error detection unit is further provided for detecting the amplitude of the feedback signal.

The present invention relates to an input/output signal synchronization method by a radio frequency unit. The input/output signal synchronization method according to the present invention comprises the steps of: generating a transmitter (Tx) input signal by adding, to a baseband signal, a test signal located at a frequency out of an operation frequency range of the radio frequency unit; collecting the Tx input signal and a Tx output signal obtained by outputting the input signal through a Tx function block; and synchronizing the Tx input signal and the Tx output signals, based on a result obtained by the collecting.

A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.

A data reception device comprises: a first data input for receiving a first data signal and a clock input for receiving a clock signal; and a stability detection circuit adapted to generate: a first error signal indicating when a data transition of the first data signal occurs during a first period at least partially before a first significant clock edge of the clock signal; and a second error signal indicating when a data transition of the first data signal occurs during a second period at least partially after the first significant clock edge of the clock signal; and a control circuit configured to generate a control signal for adjusting the sampling time of the first data signal based on said first and second error signals.

A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.

Tunable filters, cancellers, and duplexers based on passive mixers. A tunable delay cell includes passive mixers electrically coupled together for receiving an input signal and outputting a delayed signal, each passive mixer comprising a plurality of mixer switches. The tunable delay includes a control circuit for providing, to each passive mixer, a respective plurality of local oscillator (LO) signals, one to each mixer switch of each passive mixer. The control circuit is configured to vary the LO signals to cause a target frequency band of the input signal to be delayed by a target delay time in propagating through the passive mixers.

A method for logging a wellbore includes positioning a downhole tool having a downhole clock in the wellbore, logging the wellbore with the downhole tool, transmitting a surface signal from a wellbore surface to the downhole tool, and receiving the surface signal at the downhole tool. The method also includes transmitting a downhole signal from the downhole tool to the surface, receiving the downhole signal at the wellbore surface, and determining clock drift based on an arrival time of the surface signal at the downhole tool and an arrival time of the downhole signal at the wellbore surface.