H04L7/00

Baud-rate clock recovery lock point control
11569975 · 2023-01-31 · ·

A baud-rate phase detector uses two error samplers. One error sampler is used to determine whether the sampling time is too early error detection. The other is used to determine whether sampling time is too late. The early error sampler is configured to use a first threshold voltage. The late error sampler is configured to use a second threshold voltage. By adjusting the voltage difference between the first threshold voltage and the second threshold voltage, the phase difference between the local timing reference clock and the transitions of the data signal may be adjusted. The phase difference between the local timing reference clock and the transitions of the data signal may be adjusted to improve or optimize a desired receiver characteristic such as bit error rate or signal eye opening.

Enhanced time resolution for real-time clocks
11567530 · 2023-01-31 · ·

Enhanced resolution for a real-time clock is implemented, which includes a real-time clock configured to operate at a first time resolution, at least one processing unit configured to operate at a second time resolution, wherein the second time resolution has a higher frequency than the first time resolution, a memory for storing data at a location including data from the real-time clock and the at least one processing unit, an interrupt configured to load information into the memory at the location using the at least one processing unit, the interrupt further configured to operate at a frequency associated with the second time resolution, a timing service configured to read information from the memory at the location, the timing service configured to operate at the second time resolution, and a calibration module configured to re-calibrate the real-time clock.

SYSTEM AND METHOD FOR SPARSE DATA SYNCHRONIZATION AND COMMUNICATION
20230026148 · 2023-01-26 ·

Techniques, methods and system, for synchronization of sparse data signals are disclosed, comprising mixing a serial stream of sparse data signals with a serial stream of synchronization signals, to thereby add redundancy to the serial stream of sparse data signals and enable clock regeneration from a serial stream of mixed signals produced by said mixing, emulating the serial stream of synchronization signals by applying the clock regeneration to the serial stream of mixed signals, and generating a stream of parallel synchronization signals having a frequency of the serial stream of synchronization signals, deserializing the serial stream of mixed signals into a stream of parallel mixed signals having a data rate lower than a data rate of the serial signal streams, and demixing the stream of parallel synchronization signals with the stream of parallel mixed signals and thereby removing the redundancy introduced by the mixing into the sparse data signals and generating a parallel stream of demixed signals substantially synchronized with said synchronization signals.

Drift detection in timing signal forwarded from memory controller to memory device
11709525 · 2023-07-25 · ·

A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

DETECTION SYSTEM, DETECTION DEVICE, AND DETECTION METHOD

A detection system includes: a signal output unit configured to output, to a measurement target, a measurement signal that exhibits a predetermined temporal change; a signal measurement unit configured to measure a response signal, to the measurement signal, from the measurement target; a calculation unit configured to calculate an impulse response of the measurement target, based on a measurement result of the response signal measured by the signal measurement unit; and a detection unit configured to detect abnormality regarding the measurement target, based on the impulse response calculated by the calculation unit.

SYNCHRONIZING MULTIPLE INSTANCES OF PROJECTS
20230229443 · 2023-07-20 ·

The present disclosure describes techniques for synchronizing multiple instances of projects. At least one Transmission Control Protocol (TCP) connection may be established between a server computing device and at least one client computing device. At least one dual instance command may be created. The at least one dual instance command comprises data associated with a project and information indicating how to interpret the data. A plurality of instances of the project may be synchronized between the server computing device and the at least one client computing device by transmitting the at least one dual instance command between the server computing device and the at least one client computing device via the at least one TCP connection.

Storage device and storage system including the same

A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.

Adaptive private network asynchronous distributed shared memory services

A highly predicable quality shared distributed memory process is achieved using less than predicable public and private internet protocol networks as the means for communications within the processing interconnect. An adaptive private network (APN) service provides the ability for the distributed memory process to communicate data via an APN conduit service, to use high throughput paths by bandwidth allocation to higher quality paths avoiding lower quality paths, to deliver reliability via fast retransmissions on single packet loss detection, to deliver reliability and timely communication through redundancy transmissions via duplicate transmissions on high a best path and on a most independent path from the best path, to lower latency via high resolution clock synchronized path monitoring and high latency path avoidance, to monitor packet loss and provide loss prone path avoidance, and to avoid congestion by use of high resolution clock synchronized enabled congestion monitoring and avoidance.

Communication device and communication system

[Object] Effectively perform data communication [Solving Means] A communication device includes: a LINK that generates a first output signal on a basis of a first external signal from a first external device, outputs the first output signal to a second external device, generates a second output signal on a basis of a second external signal from the second external device, and outputs the second output signal to the first external device, in which each of the first output signal and the second external signal includes command information indicating content of a command transmitted from the first external device, final-destination-device-identification-information for identifying a final destination device of data transmitted from the first external device, internal address information indicating an internal address of the final destination device, data length information indicating a length of the data transmitted from the first external device, and data-end-position-information indicating an end position of the data transmitted from the first external device.

On-chip synchronous self-repairing system based on low-frequency reference signal

The present disclosure discloses an on-chip synchronous self-repairing system based on a low-frequency reference signal. The system adopts a dual-input PLL stellate coupled structure or a dual-input PLL butterfly-shaped coupled structure, and delay of the whole loop is made to be an integral multiple of the reference signal by synchronizing the transmitted reference signal with the received reference signal, so as to ensure synchronization of local oscillation signal of each IC chip. The transmission wire based on an adjustable left-handed material is used as a delay wire to connect the dual-input PLL, thereby achieving low loss and reducing the physical distance of the delay wire. The system has the advantages of small area, low loss, strong adaptability and strict synchronization in various environments.