A host side is adapted to be connected to a client side by means of a clock wire, a selection wire, a first data wire and a second data wire. The host side is configured to transmit a digital selection signal over the selection wire to the client side, the selection signal determining either an audio transmission mode or a client communication mode. Further, the host side is configured to transmit digital audio data of a first channel and a second channel over the first and the second data wire to the client side in the audio transmission mode, and to perform client communication over the first and the second data wire in the client communication mode.

LED drive control circuitry according to one embodiment outputs an LED drive control signal serving as driving a light emitting diode included in a photocoupler that performs insulation communication in synchronization with a reference clock signal. The LED drive control circuit includes a duty cycle changer that changes a duty cycle of the LED drive control signal in accordance with the reference clock signal and a signal synchronized with the reference clock signal.

In one embodiment, a synchronized communication system includes a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

A system includes a plurality of line cards and a timing card. A clock generation circuit on the timing card generates a clock signal which is pulse width modulated according to information to be transmitted. A clock line supplies the pulse width modulated clock signal to the line cards. The timing card sends a first control word to the plurality of line cards over the clock line after sending a beacon. The first control word includes a size field specifying a first length of first data following the first control word. The timing card sends time of day information over the clock line to the line cards following the first control word. The time of day information may be encrypted. A second control word follows the time of day information. One or more additional control words can follow the second control word before the next beacon.

A frequency deviation change rate computation unit (204) computes a frequency deviation change rate being a change rate per unit time of a frequency deviation between a clock frequency of a synchronization reference device serving as a reference of time synchronization and a clock frequency of a time synchronization device which performs time synchronization with the synchronization reference device. A time correction amount computation unit (205) computes a first correction amount corresponding to a static frequency deviation between the clock frequency of the synchronization reference device and the clock frequency of the time synchronization device, performs time integration of the frequency deviation change rate to compute a second correction amount corresponding to temporal transition of the frequency deviation between the clock frequency of the synchronization reference device and the clock frequency of the time synchronization device, and computes a time correction amount for correcting a time of the time synchronization device with using the first correction amount and the second correction amount. A time correction unit (206) corrects the time of the time synchronization device with using the time correction amount.

Provided are a phase detection method and apparatus for a clock signal, and a communication device. A clock signal of a clock to be detected is sampled according to sampling periods set by a sampling clock; a phase angle value corresponding to a sampled clock signal in a current sampling period is obtained according to a mapping relationship between sampled signals and phase angle values; a phase difference corresponding to the current sampling period is subtracted from the phase angle value to obtain an initial phase value of the clock to be detected in the current sampling period, wherein the phase difference is a phase difference between the clock to be detected and the sampling clock in the current sampling period; and after the sampling ends, a final phase value of the clock to be detected is obtained according to initial phase values obtained in respective sampling periods.

A signal correction apparatus of an SBW system may include: a command signal receiving/transmitting unit configured to receive a command signal transmitted through a vehicle communication network by an upper level apparatus, and transmit a command signal, obtained by correcting the linearity of the received command signal, to a lower level apparatus through the vehicle communication network; a buffer unit configured to store the command signal, received through the command signal transmitting/receiving unit, as an original signal; and a control unit configured to generate a command signal whose linearity is corrected, by correcting the linearity of the original signal by using the original signal stored as the command signal in the buffer unit and a command signal obtained by delaying the command signal, stored in the buffer unit, by designated one unit time.

Adaptive payload extraction in wireless communications involving multi-access address packets are described herein. A device can be configured to detect a synchronization sequence of a nested data packet, the nested data packet having synchronization sequences placed in series ahead of a payload, the synchronization sequences including the synchronization sequence; evaluate blocks after the synchronization sequence in the nested data packet to identify the blocks as either additional ones of the synchronization sequences or the payload in the nested data packet; and extract the payload.

A data transfer circuit (40) according to the invention includes a memory (41) configured to write data in accordance with a write pointer in synchronization with a first clock, and read out the data in accordance with a readout pointer in synchronization with a second clock, a clock generation circuit (44) configured to generate the second clock by multiplying a reference clock by a rational number N, a frequency error estimation circuit (42) configured to estimate a frequency error between the first clock and the second clock based on a change amount of a pointer difference between the write pointer and the readout pointer, and an adjustment circuit (43) configured to output, as an adjustment multiple ΔN, a value obtained by dividing the estimated frequency error by a frequency of the reference clock. The clock generation circuit (44) generates the second clock by multiplying the reference clock by a rational number (N+ΔN) using the adjustment multiple ΔN output from the adjustment circuit (43). A data transfer circuit capable of speeding up clock synchronization can be provided.