Methods, systems, and devices for efficient fabrication of memory structures are described. A multi-deck memory device may be fabricated using a sequence of fabrication steps that include depositing a first metal layer, depositing a cell layer on the first metal layer to form memory cells of the first memory deck, and depositing a second metal layer on the cell layer. The second metal layer may be deposited using a single deposition process rather than using multiple deposition processes. A second memory deck may be formed on the second metal layer such that stacked memory cells from the first and second deck share the use of the second metal layer. Using a single deposition process for the second metal layer may decrease the quantity of fabrication steps used to fabricate the multi-deck memory array and reduce or eliminate the exposure of the cell material to metal etchants.

Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate including a peripheral region, wherein the peripheral region includes a wire lead-out area, and the substrate is arranged with a plurality of discrete bit line structures; a dielectric layer formed between the adjacent bit line structures, wherein the peripheral region is arranged with a first contact hole; a wire lead-out area with a second through hole; a filling layer filling part of a first contact hole, wherein a remaining part of the first contact hole is defined as a first through hole; a first conductive layer located in the first through hole and the second through hole; and a conductive connecting wire located over the dielectric layer and being in contact with the first conductive layer in the wire lead-out area.

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate including a peripheral region, wherein the peripheral region includes a wire lead-out area, and the substrate is arranged with a plurality of discrete bit line structures; a dielectric layer formed between the adjacent bit line structures, wherein the peripheral region is arranged with a first contact hole; a wire lead-out area with a second through hole; a filling layer filling part of a first contact hole, wherein a remaining part of the first contact hole is defined as a first through hole; a first conductive layer located in the first through hole and the second through hole; and a conductive connecting wire located over the dielectric layer and being in contact with the first conductive layer in the wire lead-out area.

A method for forming a semiconductor device includes the steps of providing a substrate having a memory region and a logic region, forming a memory stack structure on the memory region, forming a passivation layer covering a top surface and sidewalls of the memory stack structure, forming a first interlayer dielectric layer on the passivation layer, performing a post-polishing etching back process to remove a portion of the first interlayer dielectric layer and a portion of the passivation layer on the top surface of the memory stack structure, forming a second interlayer dielectric layer on the first interlayer dielectric layer and directly contacting the passivation layer, and forming an upper contact structure through the second interlayer dielectric layer and the passivation layer on the top surface of the memory stack structure to contact the memory stack structure.

A semiconductor device and a related fabrication method are provided. The semiconductor device includes a conductive line on a substrate, a capping pattern that extends along an upper surface of the conductive line, a spacer structure that extends along a side surface of the conductive line and a side surface of the capping pattern, a buried contact electrically connected to the substrate, on a side surface of the spacer structure, a barrier conductive film extending along the buried contact and the spacer structure, and a landing pad electrically connected to the buried contact, on the barrier conductive film and the capping pattern, wherein an upper part of the spacer structure includes a spacer recess that is lower than or equal to an uppermost surface of the capping pattern, and the barrier conductive film extends along the spacer recess and does not cover the uppermost surface of the capping pattern.

A semiconductor device including a substrate, lower electrodes disposed on the substrate, at least one support layer in contact with the lower electrodes, a dielectric layer disposed on the lower electrodes, an upper electrode disposed on the dielectric layer, a first interfacial film between the lower electrodes and the dielectric layer, and a second interfacial film between the upper electrode and the dielectric layer. At least one of the first and second interfacial films includes a plurality of layers, wherein the plurality of layers include a first metal element, and a second metal element, and at least one of oxygen \and nitrogen. The lower electrodes include the first metal element. A first region of the first interfacial film includes the second metal element at a first concentration and a second region of the first interfacial film includes the second metal element at a second concentration different from the first concentration.

A fabricating equipment and method for a semiconductor device is provided. The fabricating equipment comprises a process chamber including an internal space, a substrate support which supports a substrate including a first film and a second film, inside the internal space, a nozzle which is placed on the substrate support and supplies a process gas, a first heater which is placed inside the substrate support and heats the substrate and a second heater which generates one of waves of a first frequency and waves of a second frequency to differentially heat the first film and the second film.

A semiconductor device includes a substrate including first and second active regions; a bitline structure extending in one direction on the substrate, the bitline structure being electrically connected to the first active region; a storage node contact on a sidewall of the bitline structure, the storage node contact being electrically connected to the second active region; a spacer structure between the bitline structure and the storage node contact; a landing pad on the storage node contact, the landing pad being in contact with a sidewall of the spacer structure; and a capacitor structure electrically connected to the landing pad, wherein the spacer structure includes a first spacer, a second spacer, a third spacer, and a fourth spacer, sequentially stacked on the sidewall of the bitline structure, the second spacer is an air spacer, and the third spacer has a thickness that is less than a thickness of the first spacer.

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The manufacturing method of a semiconductor structure includes: providing a substrate, where a plurality of first electrodes arranged at intervals are formed on the substrate; forming a dielectric layer on surfaces of the first electrodes, where a duration of a single purge required for forming the dielectric layer is greater than or equal to a first threshold; or forming a multi-dielectric-layers stack on the surfaces of the first electrodes, where a duration of a single purge required for forming a first dielectric layer of the multi-dielectric-layers stack is greater than or equal to the first threshold. The manufacturing method can improve the manufacturing process of the capacitor in the semiconductor structure, to avoid defects such as current leakages and relatively small capacitance values, thereby ensuring the electrical performance of the semiconductor structure.