An approach to provide a semiconductor structure for a phase change memory cell with a first liner material surrounding a sidewall of a hole in a dielectric material where the hole in the dielectric is on a bottom electrode in the dielectric material. The semiconductor structure includes a layer of a second liner material on the first liner material, where the second liner material has an improved contact resistance to a phase change material. The semiconductor structure includes the phase change material abutting the layer of the second liner material on the first liner material. The phase change material fills the hole in the dielectric material. The second liner material that is between the phase change material and the first liner material provides a lower contact resistivity with the phase change material in the crystalline phase than the first liner material.

Disclosed are a self-healing memory device including a lower electrode; a polymer nanocomposite layer formed on the lower electrode, wherein, when a structural defect occurs, the polymer nanocomposite layer repairs the structural defect and restores a memory function damaged due to the structural defect through a self-healing mechanism characterized by movement of a polymer material and hydrogen bonding; and an upper electrode formed on the polymer nanocomposite layer and a method of manufacturing the self-healing memory device.

A resistive memory device may include a first and second signal lines, a memory layer, a first and second drivers, and a first contact structure. The first signal line may include a first contact node. The first and second signal lines may intersect. The second signal line may include a second contact node. The memory layer may be at an intersecting portion between the first and second signal lines and the memory layer may be configured to change its resistance based on a voltage difference between the first and second signal lines. The first and second drivers may be configured to selectively provide the first contact node with a first power voltage and a second power voltage different from the first power voltage, respectively. The first contact structure may be configured to electrically connect the first contact node with the first and second drivers.

There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor memory device includes: a gate stack structure including a plurality of interlayer insulating layers and a plurality of conductive patterns, which are alternately stacked in a vertical direction; a dummy stack structure including a plurality of dummy interlayer insulating layers and a plurality of sacrificial layers, which are alternately stacked in the vertical direction, the dummy stack structure being disposed at a level at which the gate stack structure is disposed; a channel structure penetrating the gate stack structure; a memory layer disposed between each of the plurality of conductive patterns and the channel structure; and a dummy pillar penetrating a portion of the dummy stack structure with a length less than a length of the channel structure in the vertical direction.

A semiconductor device including at least one memory cell is provided. The memory cell includes: a first electrode layer; a second electrode layer; a selection element layer coupled between the first electrode layer and the second electrode layer; and an insulating layer coupled between the first electrode layer and the second electrode such that a side surface of the insulating layer is in contact with a side surface of the selection element layer, wherein the selection element layer includes an insulating material doped with a first element, and wherein the insulating layer includes the insulating material doped with the first element at a lower concentration than the selection element layer, or the insulating material not doped with the first element.

A semiconductor device that includes: first conductive lines; second conductive lines disposed over the first lines to be spaced apart from the first lines; and a selector layer disposed between the first lines and the second lines and including a dielectric material and a dopant doped with a uniform dopant profile.

A semiconductor device that includes: first conductive lines; second conductive lines disposed over the first lines to be spaced apart from the first lines; and a selector layer disposed between the first lines and the second lines and including a dielectric material and a dopant doped with a uniform dopant profile.

The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.

A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) with increased on-state current obtained through a parasitic bipolar junction transistor (BJT) of the MOSFET. Methods of operating the MOSFET as a memory cell or a memory array select transistor are provided.

A nonvolatile memory device includes a resistance switching layer, a gate on the resistance switching layer, a gate oxide layer between the resistance switching layer and the gate, and a source and a drain, spaced apart from each other, on the resistance switching layer. A resistance value of the resistance switching layer is changed based on an illumination of light irradiated onto the resistance switching layer and is maintained as a changed resistance value.