A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including a plurality of first transistors and at least one metal layer, where the at least one metal layer overlays the first single crystal layer, and where the at least one metal layer includes interconnects between the plurality of first transistors, the interconnects between the plurality of first transistors include forming first control circuits; a second level overlaying the at least one metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the plurality of second transistors, where the third level includes a plurality of second memory cells, the second memory cells each including at least one of the plurality of third transistors, where at least one of the plurality of second memory cells is at least partially atop of the first control circuits, where the first control circuits are adapted to control data written to at least one of the plurality of second memory cells; and where the plurality of second transistors are horizontally oriented transistors.

Embodiments of methods of filling features with molybdenum (Mo) include depositing a first layer of Mo in a feature including an opening and an interior and non-conformally treating the first layer such that regions near the opening preferentially treated over regions in the interior. In some embodiments, a second Mo layer is deposited on the treated first layer. Embodiments of methods of filling features with Mo include controlling Mo precursor flux to transition between conformal and non-conformal fill.

A semiconductor memory device includes a memory string, first wirings electrically connected to the memory string, second wirings electrically connected to the first wirings, transistors electrically connected between the first wirings and the second wirings, and a third wiring connected to gate electrodes of the transistors in common. The memory string includes memory transistors connected in series. Gate electrodes of the memory transistors are connected to the first wirings. The semiconductor memory device executes a first read operation in response to an input of a first command set, and executes a second read operation in response to an input of a second command set. A first voltage that turns the transistors ON is applied to the third wiring from an end of the first read operation to a start of the second read operation.

Charge storage and sensing devices having a tunnel diode operable to sense charges stored in a charge storage structure are provided. In some embodiments, a device includes a substrate, a charge storage device on the substrate, and tunnel diode on the substrate adjacent to the charge storage device. The tunnel diode includes a tunnel diode dielectric layer on the substrate, and a tunnel diode electrode on the tunnel diode dielectric layer. A substrate electrode is disposed on the doped region of the substrate, and the tunnel diode electrode is positioned between the charge storage device and the substrate electrode.

A thickness prediction network learning method includes measuring spectrums of optical characteristics of a plurality of semiconductor structures each including a substrate and first and second semiconductor material layers alternately stacked thereon to generate sets of spectrum measurement data, measuring thicknesses of the first and second semiconductor material layers to generate sets of thickness data, training a simulation network using the sets of spectrum measurement data and the sets of thickness data, generating sets of spectrum simulation data of spectrums of the optical characteristics of a plurality of virtual semiconductor structures based on thicknesses of first and second virtual semiconductor material layers using the simulation network, each of the first and second virtual semiconductor layers including the same material as the first and second semiconductor material layers, respectively; and training a thickness prediction network by using the sets of spectrum measurement data and the sets of spectrum simulation data.

A 3D semiconductor device including: a first level including a first single crystal layer, the first level including a plurality of first transistors and at least one first metal layer, where the at least one first metal layer overlays the first single crystal layer, and where the at least one first metal layer includes interconnects between the first transistors forming first control circuits; a second metal layer overlaying the at least one first metal layer; a second level overlaying the second metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the second transistors, where the third level includes second memory cells, the second memory cells each including third transistors.

A semiconductor device having a three-dimensional (3D) structure is disclosed. The semiconductor device includes a first substrate layer including a logic circuit, and a plurality of second substrate layers stacked on the first substrate layer, the plurality of second substrate layers including a memory cell array. Each of the plurality of second substrate layers includes, a transfer circuit, coupled to a row line of the memory cell array, that is disposed over the second substrate layer and selectively coupled to a global row line.

Molybdenum is etched in a highly controllable manner by performing one or more etch cycles, where each cycle involves exposing the substrate having a molybdenum layer to an oxygen-containing reactant to form molybdenum oxide followed by treatment with boron trichloride to convert molybdenum oxide to a volatile molybdenum oxychloride with subsequent treatment of the substrate with a fluorine-containing reactant to remove boron oxide that has formed in a previous reaction, from the surface of the substrate. In some embodiments the method is performed in an absence of plasma and results in a substantially isotropic etching. The method can be used in a variety of applications in semiconductor processing, such as in wordline isolation in 3D NAND fabrication.

A memory system includes a first memory cell array which is a nonvolatile memory cell array, a controller configured to control read and write of data, a first data latch group used for input and output of the data between the controller and the first memory cell array, and at least one second data latch group in which stored data is maintained when the data is read from the first memory cell array by the controller. The controller is configured to store management information in the at least one second data latch group when or before executing a read process for the data from the first memory cell array, the management information being in a second memory cell array and used for read of the data.

A method for fabricating a memory is provided. The method includes providing a bit-line layer, on a semiconductor substrate and having bit lines arranged in the bit-line layer; providing a shielding layer, on the bit-line layer and having a conductive shielding structure arranged in the shielding layer. The conductive shielding structure is within a top-view projection area of the bit lines and is grounded. The method further includes providing a word-line layer, on the shielding layer and having word lines arranged in the word-line layer.