An image sensor includes: a photoelectric conversion film that performs photoelectric conversion on light having entered therein; at least two electrodes, including a first electrode and a second electrode, disposed at a surface of the photoelectric conversion film; and at least two electrodes, including a third electrode and a fourth electrode, disposed at another surface of the photoelectric conversion film.

The present disclosure generally relates to multi-switch storage cells (MSSCs), three-dimensional MSSC arrays, and three-dimensional MSSC memory. Multi-switch storage cells include a cell select device, multiple resistive change elements, and an intracell wiring electrically connecting the multiple resistive change elements together and to the cell select device. MSSC arrays are designed (architected) and operated to prevent inter-cell (sneak path) currents between multi-switch storage cells, which prevents stored data disturb from adjacent cells and adjacent cell data pattern sensitivity. Additionally, READ and WRITE operations may be performed on one of the multiple resistive change elements in a multi-switch storage cell without disturbing the stored data in the remaining resistive change elements. However, controlled parasitic currents may flow in the remaining resistive change elements within the cell. Isolating each multi-switch storage cell in a three-dimensional MSSC array, enables in-memory computing for applications such as data processing for machine learning and artificial intelligence.

An integrated circuit including a first circuit module and a second circuit module is provided. A layer stack may include one or multiple metal layers with a power segment and a ground segment connected to the first circuit module and the second circuit module, which form a resonant current loop. A pickup loop may be inductively coupled to the resonant current loop to dampen its resonance, thereby making the IC compliant with its EMC requirements or removing functional errors such as problems in the signal or power integrity.

A three-dimensional electric element 10 comprises four or more nonlinear units 11 each having nonlinear current-voltage characteristics and an electric conductor 12 connecting the nonlinear units 11, and the nonlinear units 11 are arranged in a three-dimensional manner. A machine learning system 20 comprises a three-dimensional electric element 10 that includes four or more nonlinear units 11 each having nonlinear current-voltage characteristics and an electric conductor 12 connecting the nonlinear units 11 being arranged in a three-dimensional manner, and an input electrode 13 and an output electrode 14, the input electrode 13 and the output electrode 14 are connected to the three-dimensional electric element 10.

A solid-state imaging element according to an embodiment of the present disclosure includes a first electrode including a plurality of electrodes, a second electrode opposed to the first electrode, and a photoelectric conversion layer provided between the first electrode and the second electrode, and the first electrode has, at least in a portion, an overlap section where the plurality of electrodes overlap each other with a first insulation layer interposed therebetween.

The invention provides an optoelectronic device comprising: (i) a porous dielectric scaffold material; and (ii) a semiconductor having a band gap of less than or equal to 3.0 eV, in contact with the scaffold material. Typically the semiconductor, which may be a perovskite, is disposed on the surface of the porous dielectric scaffold material, so that it is supported on the surfaces of pores within the scaffold. In one embodiment, the optoelectronic device is an optoelectronic device which comprises a photoactive layer, wherein the photo-active layer comprises: (a) said porous dielectric scaffold material; (b) said semiconductor; and (c) a charge transporting material. The invention further provides the use, as a photoactive material in an optoelectronic device, of: (i) a porous dielectric scaffold material; and (ii) a semi-conductor having a band gap of less than or equal to 3.0 eV, in contact with the scaffold material. Further provided is the use of a layer comprising: (i) a porous dielectric scaffold material; and (ii) a semiconductor having a band gap of less than or equal to 3.0 eV, in contact with the scaffold material; as a photoactive layer in an optoelectronic device. In another aspect, the invention provides a photoactive layer for an optoelectronic device comprising (a) a porous dielectric scaffold material; (b) a semiconductor having a band gap of less than or equal to 3.0 eV, in contact with the scaffold material; and (c) a charge transporting material.

A solid-state imaging element according to an embodiment of the present disclosure includes: a first electrode including a plurality of electrodes; a second electrode opposed to the first electrode; and a photoelectric conversion layer provided between the first electrode and the second electrode, and the first electrode has, at least in a portion, an overlap section where the plurality of electrodes overlap each other with a first insulation layer interposed therebetween.

An electronic display having pixels and control circuitry to drive the pixels to display image data even during relatively long presentation times without visual artifacts, such as flicker, are provided. The control circuitry may cause the pixel to perform a threshold voltage sampling and pixel programming phase to store image data for the pixel while accounting for a first threshold voltage of the first transistor. Afterward, an on-bias stress phase may cause a threshold voltage of the first transistor of the plurality of transistors to reach a second threshold voltage. Following the on-bias stress phase, a first emission phase may cause the light-emitting diode to emit light in accordance with the image data, and subsequent on-bias stress phases and subsequent emission phases for the duration of the presentation time may take place without a visible flicker artifact.

Programmable memory devices having a cross-point array of polymer junctions with individually-programmed conductances are provided. In one aspect, a method of forming a memory device includes: forming first metal lines on an insulating substrate; forming polymeric resistance elements on the first metal lines; and forming second metal lines over the polymeric resistance elements with a single one of the polymeric resistance elements present at each intersection of the first/second metal lines forming a cross-point array. A memory device and a method of operating a memory device are also provided.

A method includes forming a circuit region over a substrate. The circuit region includes at least one active region extending along a first direction, and at least one gate region extending across the at least one active region and along a second direction transverse to the first direction. At least one first input/output (TO) pattern and at least one second TO pattern are correspondingly formed in different first and second metal layers to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first TO pattern extends along a third direction oblique to both the first direction and the second direction. The at least one second TO pattern extends along a fourth direction oblique to both the first direction and the second direction, the fourth direction transverse to the third direction.