A memory device includes a memory material portion, and an ovonic threshold switch selector element. The ovonic threshold switch selector element includes a first carbon-containing electrode comprising carbon and a metal, a second carbon-containing electrode comprising the carbon and the metal, and an ovonic threshold switch material portion located between the first electrode and the second electrode.

A variable resistance memory device includes a stacking pattern disposed on a substrate, a vertical structure extends in a first direction, which is perpendicular to a top surface of the substrate, and penetrates the stacking pattern, and a horizontal conductive line disposed adjacent to the stacking pattern and extending in a second direction that is parallel to the top surface of the substrate. The vertical structure includes a vertical conductive line penetrating the stacking pattern, a variable resistance element enclosing the vertical conductive line, and a selection element interposed between the vertical conductive line and the variable resistance element. Each of the vertical conductive line, the variable resistance element, and the selection element extends in the first direction. The stacking pattern is electrically connected to the horizontal conductive line and extends along the horizontal conductive line and in the second direction.

Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.

Phase change memory devices and methods of forming the same include forming a fin structure from a first material. A phase change memory cell is formed around the fin structure, using a phase change material that includes two solid state phases at an operational temperature.

A switching device includes first and second RF terminals disposed over a substrate, one or more strips of phase change material connected between the first and second RF terminals, a region of thermally insulating material that separates the one or more strips of phase change material from the substrate, and a heater structure comprising one or more heating elements that are configured to control a conductive connection between the first and second RF terminals by applying heat to the one or more strips of phase change material. Each of the one or more strips of phase change material includes a first outer face and a second outer face opposite from the first outer face. For each of the one or more strips of phase change material, at least portions of both of the first and second outer faces are disposed against one of the heating elements.

A phase change resistive memory includes an upper electrode; a lower electrode; a layer made of an active material, called an active layer; the memory passing from a highly resistive state to a weakly resistive state by application of a voltage or a current between the upper electrode and the lower electrode and wherein the material of the active layer is a ternary composed of germanium Ge, tellurium Te and antimony Sb, the ternary including between 60 and 66% of antimony Sb.

A phase-change memory (PCM) device includes a first electrode, a second electrode, a memory layer, and a heater. The memory layer includes a phase-change material and is electrically coupled between the first electrode and the second electrode. The heater is arranged near the memory layer and is configured to heat a programming region of the memory layer in response to an electric current that passes through the heater. The heater is coupled to a power source via an electric current path that does not pass through the memory layer.

The present disclosure provides a 1T1R resistive random access memory and a manufacturing method thereof, and a device. The 1T1R resistive random access memory includes: a memory cell array composed of multiple 1T1R resistive random access memory cells, each 1T1R resistive random access memory cell including a transistor and a resistance switching device (30). The transistor includes a channel layer (201), a gate layer (204) insulated from the channel layer (201), and a drain layer (203) and a source layer (202) disposed on the channel layer (201), and the drain layer (203) and the source layer (202) are vertically distributed on the channel layer (201). The resistance change device (30) is disposed near the drain layer (203). The disclosure reduces the area of a transistor, thereby significantly improving the memory density of the resistive random access memory.

Devices with settable resistance and methods of forming the same include forming vertical dielectric structures from heterogeneous dielectric materials on a first electrode. A second electrode is formed on the vertical dielectric structures.

A chalcogenide material may include germanium (Ge), arsenic (As), selenium (Se) and from 0.5 to 10 at % of at least one group 13 element. A variable resistance memory device may include a first electrode, a second electrode, and a chalcogenide film interposed between the first electrode and the second electrode and including from 0.5 to 10 at % of at least one group 13 element. In addition, an electronic device may include a semiconductor memory. The semiconductor memory may include a column line, a row line intersecting the column line, and a memory cell positioned between the column line and the row line, wherein the memory cell comprises a chalcogenide film including germanium (Ge), arsenic (As), selenium (Se), and from 0.5 to 10 at % of at least one group 13 element.