Disclosed is a method for the manufacture of a CEM device comprising forming a thin film of a correlated electron material having a predetermined electrical impedance when the CEM device in its relatively conductive (low impedance) state, wherein the forming of the CEM thin film comprises forming a d- or f-block metal or metal compound doped by a physical or chemical vapor deposition with a predetermined amount of a dopant comprising a back-donating ligand for the metal.

Disclosed is a method for the manufacture of a CEM device comprising forming a thin film of a correlated electron material having a predetermined electrical impedance when the CEM device in its relatively conductive (low impedance) state, wherein the forming of the CEM thin film comprises forming a d- or f-block metal or metal compound doped by a physical or chemical vapour deposition with a predetermined amount of a dopant comprising a back-donating ligand for the metal.

The present disclosure is drawn to, among other things, a method of forming a semiconductor shield from a stock material having a thickness. In some aspects the methods includes providing a first layer of material on a first surface of the stock material, wherein at least a portion of the first layer of material includes a first window that exposes a portion of the first surface; providing a second layer of material on a second surface of the stock material, wherein the second surface of the stock material is spaced from the first surface by the thickness of the stock material, and wherein at least portion of the second layer of material includes a second window that exposes a portion of the second surface; and selectively removing a portion of the stock material exposed at the first or second windows, wherein the portion removed includes less than an entirety of the thickness of the stock material.

An integrated circuit includes a substrate, a pad electrode disposed on the substrate, and a passivation layer disposed on the pad electrode and including an organic insulating material. The integrated circuit further includes a bump electrode disposed on the passivation layer and connected to the pad electrode through a contact hole. The passivation layer includes an insulating portion having a first thickness and covering an adjacent edge region of the pad electrode and the substrate, and a bump portion having a second thickness, that is greater than the first thickness, and covering a center portion of the pad electrode.

A dual resonator chip, includes a kilohertz frequency resonator in the chip and a megahertz frequency resonator in the same chip, wherein the kilohertz frequency resonator and the megahertz frequency resonator are MEMS resonators.

A dual resonator chip, includes a kilohertz frequency resonator in the chip and a megahertz frequency resonator in the same chip, wherein the kilohertz frequency resonator and the megahertz frequency resonator are MEMS resonators.

The present disclosure is drawn to, among other things, a method of forming a semiconductor shield from a stock material having a thickness. In some aspects the methods includes providing a first layer of material on a first surface of the stock material, wherein at least a portion of the first layer of material includes a first window that exposes a portion of the first surface; providing a second layer of material on a second surface of the stock material, wherein the second surface of the stock material is spaced from the first surface by the thickness of the stock material, and wherein at least portion of the second layer of material includes a second window that exposes a portion of the second surface; and selectively removing a portion of the stock material exposed at the first or second windows, wherein the portion removed includes less than an entirety of the thickness of the stock material.

A semiconductor device is provided. The semiconductor device includes a substrate which includes a cell region including first and second regions, and a peri region more adjacent to the second region than adjacent to the first region, first and second lower electrodes disposed in the first and second regions, respectively, first and second lower support patterns disposed on outer walls of the first and second lower electrodes, respectively, an upper support pattern disposed on outer walls of the first and second lower electrodes, and being on and spaced apart from the first and second lower support patterns, a dielectric layer disposed on surfaces of the first and second lower electrodes, the first and second lower support patterns, and the upper support pattern, and an upper electrode disposed on a surface of the dielectric layer, wherein thickness of the first lower support pattern is smaller than thickness of the second lower support pattern.

The present application relates to a capacitor device and a manufacturing method thereof, and a memory. forming a first capacitor structure on a substrate, includes: a first capacitor dielectric layer, a first upper electrode, a plurality of first lower electrodes arranged at intervals; the first capacitor dielectric layer at least covers sidewalls of the first lower electrodes, and the first upper electrode fills up gaps at an outer side of the first capacitor dielectric layer; forming a second capacitor structure on the first capacitor structure, the second capacitor structure includes a second capacitor dielectric layer, a second upper electrode, and a plurality of second lower electrodes arranged at intervals; the second lower electrodes are of a U-shaped structure, bottoms of the second lower electrodes are in contact with tops of the first lower electrodes, the second capacitor dielectric layer is at least located on surfaces of the second lower electrodes.

A device for generating thrust using the dynamic Casimir effect comprising: an epitaxial stack of closely spaced parallel semiconductor laminae; and a voltage source; wherein each said semiconductor lamina is connected to said voltage source such that said voltage source can apply voltage to each semiconductor lamina.