H10N99/00

NONVOLATILE MEMORY CELL, NONVOLATILE MEMORY CELL ARRAY, AND INFORMATION WRITING METHOD OF NONVOLATILE MEMORY CELL ARRAY
20220262420 · 2022-08-18 ·

A nonvolatile memory cell includes a resistance-change nonvolatile memory element 50 and a selection transistor TR. One end of the nonvolatile memory element 50 is connected to one source/drain region 15A of the selection transistor TR and is connected to a write line WR. The other source/drain region 15B of the selection transistor TR is connected to a select line SL. The other end of the nonvolatile memory element 50 is connected to a bit line BL.

INSULATION LAYER FORMATION METHOD, MEMBER WITH INSULATION LAYER, RESISTANCE MEASUREMENT METHOD AND JUNCTION RECTIFIER
20220251712 · 2022-08-11 ·

An insulation layer formation method comprises: a first step in which a surface treatment is applied to a base material to form thereon a high-resistance layer having high electric resistivity; a second step in which metal plating parts are formed on the base material that has undergone the first step in such a manner as to allow a high-resistance layer to be formed thereon; and a third process in which a high-resistance layer is formed on the base material that has undergone the second step.

Storage ring quantum computer
11839168 · 2023-12-05 · ·

A system and method for storing information in a quantum computer using a quantum storage ring. The method comprises cooling ions in the quantum storage ring to a low temperature; and binding the ions into a lattice structure, forming an ion Coulomb crystal.

Individually tunable quantum dots in all-van der waals heterostructures

Apparatus, methods, and systems are disclosed for robust scalable topological quantum computing. Quantum dots are fabricated as van der Waals heterostructures, supporting localized topological phases and non-Abelian anyons (quasiparticles). Large bandgaps provide noise immunity. Three-dot structures include an intermediate quantum dot between two computational quantum dots. With the intermediate quantum dot in an OFF state, quasiparticles at the computational quantum dots can be isolated, with long lifetimes. Alternatively, the intermediate quantum dot can be controlled to decrease the quasiparticle tunneling barrier, enabling fast computing operations. A computationally universal suite of operations includes quasiparticle initialization, braiding, fusion, and readout of fused quasiparticle states, with, optionally, transport or tunable interactions—all topologically protected. Robust qubits can be operated without error correction. Quasilinear arrays of quantum dots or qubits can be scaled arbitrarily, up to resource limits, and large-scale topological quantum computers can be realized. Extensive two-dimensional arrays can also be used.

Ultrasensitive sensor based on a piezoelectric transistor

Methods of using and making chemical sensors include exposing a functionalized electrode to a substance to be tested. The functionalized electrode is electrically connected to a sensor having a piezoelectric element and a piezoresistive element. A voltage on the functionalized electrode controls a resistance of the piezoresistive element. A current is measured passing through the piezoresistive element. The presence of the analyte is determined based on the measured current.

Compound semiconductor and use thereof

A novel compound semiconductor which can be used for a solar cell, a thermoelectric material, or the like, and the use thereof.

Circuit element, storage device, electronic equipment, method of writing information into circuit element, and method of reading information from circuit element

Provided is a circuit element that includes paired inert electrodes, and a switch layer provided between the paired inert electrodes, that functions as a selection element and a storage element as a single layer, and having a differential negative resistance region in a current-voltage characteristic.

Logic integrated circuit

A logic integrated circuit includes a switch cell array. The switch cell array includes: a plurality of first wirings extending in a first direction; a plurality of second wirings extending in a second direction; a switch cell including a unit element including two serially connected resistance-changing elements, and a cell transistor to be connected to a shared terminal of the two resistance-changing elements; and a bit line to which the shared terminal is connected via the cell transistor. Two of the switch cells adjacent to each other in the first direction are each connected to the different first wiring and second wiring, and share the bit line, and a diffusion layer to which the bit line is connected.

TOPOLOGICAL QUANTUM FIELD EFFECT TRANSISTOR
20230413700 · 2023-12-21 ·

Disclosed herein is a structure comprising: a gate electrode, a dielectric layer, and a planar layer of a topological material being separated from the gate electrode by at least the dielectric layer, and having a contact interface with the dielectric layer to generate an electric field-controlled Rashba spin-orbit interaction on application of an electric field thereto, wherein the topological material exhibits a topological phase transition between a trivial state and a non-trivial state at a critical electric field strength on application of the electric field, wherein the gate electrode is configured to apply the electric field across the planar layer in a direction perpendicular to a plane of the planar layer; and wherein the topological material exhibits a change in bandgap, in the presence of the electric field, having a spin-dependent contribution represented by a proportionality constant R and a non-spin-dependent contribution represented by a proportionality constant v; and wherein R>.sub.v/3.

Piezoelectronic device with novel force amplification

A piezoelectronic device with novel force amplification includes a first electrode; a piezoelectric layer disposed on the first electrode; a second electrode disposed on the piezoelectric layer; an insulator disposed on the second electrode; a piezoresistive layer disposed on the insulator; a third electrode disposed on the insulator; a fourth electrode disposed on the insulator; a semi-rigid housing surrounding the layers and the electrodes; wherein the semi-rigid housing is in contact with the first, third, and fourth electrodes and the piezoresistive layer; wherein the semi-rigid housing includes a void. The third and fourth electrodes are on the same plane and separated from each other in the transverse direction by a distance.