A method of operating a device includes: (1) providing a film of a semimetal in a first topological phase; and (2) inducing interlayer shear oscillation of the semimetal within the film, wherein the interlayer shear oscillation induces the semimetal to transition to a different, second topological phase.

A vacuum vessel supporting superconducting computing device environments includes a vacuum vessel having a cylindrical chamber defined by an internal frame, including upper and lower mounting rings, and at least two vertical support members disposed between the upper and lower mounting rings. The chamber is further defined by an upper plate releasably attached to the upper mounting ring, a lower plate releasably attached to the lower mounting plate, at least two side walls releasably attached to the upper mounting ring, the lower mounting ring and at least two vertical support members. Seal elements are disposed between the upper plate and the upper mounting ring, the lower plate and the lower mounting ring, and each side wall and the internal frame.

A logic integrated circuit includes a switch cell array. The switch cell array includes: a plurality of first wirings extending in a first direction; a plurality of second wirings extending in a second direction; a switch cell including a unit element including two serially connected resistance-changing elements, and a cell transistor to be connected to a shared terminal of the two resistance-changing elements; and a bit line to which the shared terminal is connected via the cell transistor. Two of the switch cells adjacent to each other in the first direction are each connected to the different first wiring and second wiring, and share the bit line, and a diffusion layer to which the bit line is connected.

A thermal emitter including a substrate and a grating arranged atop the substrate, the grating includes a plurality of equidistant structures having a cross-section with a trapezoid shape. Material of the substrate and the grating converts incoming heat into radiation.

A micromechanical moisture-sensor device and a corresponding manufacturing method. The micromechanical moisture-sensor device is equipped with a first electrode device situated on the substrate; a second electrode device situated on the substrate; an electrical insulation device situated between the first electrode device and the second electrode device which includes a first area, which is in contact with the first electrode device and the second electrode device, and which includes a second area, which is exposed by the first electrode device and the second electrode device; a moisture-sensitive functional layer, which is applied across the first electrode device and the second electrode device and the second area of the insulation device lying between them in such a way that it forms a moisture-sensitive resistive electrical shunt at least in some areas between the first electrode device and the second electrode device.

A method of operating a device includes: (1) providing a film of a semimetal in a first topological phase; and (2) inducing interlayer shear oscillation of the semimetal within the film, wherein the interlayer shear oscillation induces the semimetal to transition to a different, second topological phase.

The electricity storage device includes: a first conductivity-type first oxide semiconductor; a solid electrolyte layer disposed on the first oxide semiconductor layer, the solid electrolyte layer including a solid electrolyte enabling proton movement; an insulator layer disposed between the solid electrolyte layer and the first oxide semiconductor layer, the insulator layer including an insulating material; and a second conductivity-type second oxide semiconductor layer disposed on the solid electrolyte layer. Provided is the electricity storage device having the increased electricity storage capacity and improved reliability that can be charged without degradation even when the charging voltage is increased.

A piezoresistive transistor device includes a first transistor cell having a first piezoelectric material body and a first piezoresistive material body arranged in a stacked configuration. A first electrical resistance of the first piezoresistive material body is dependent upon a voltage applied across the first piezoelectric material body by way of a pressure applied by the first piezoelectric material body to the first piezoresistive material body. A second transistor cell includes a second piezoelectric material body and a second piezoresistive material body arranged in a stacked configuration. A second electrical resistance of the second piezoresistive material body is dependent upon a voltage applied across the second piezoelectric material body by way of a pressure applied by the second piezoelectric material body to the second piezoresistive material body. An internal electrical interconnect is configured to electrically connect the first electrical resistance and the second electrical resistance in series or in parallel.

Techniques facilitating frequency allocation in multi-qubit circuits are provided. In one example, a computer-implemented method comprises determining, by a device operatively coupled to a processor, an estimated fabrication yield associated with respective qubit chip configurations by conducting simulations of the respective qubit chip configurations at respective frequency offsets; and selecting, by the device, a qubit chip configuration from among the respective qubit chip configurations based on the estimated fabrication yield associated with the respective qubit chip configurations.

Provided is a monolithic metal-insulator transition device. The monolithic metal-insulator transition device includes a substrate including a driving region and a switching region, first and second source/drain regions on the driving region, a gate electrode between the first and second source/drain regions, an inlet well region formed adjacent to an upper surface of the substrate on the switching region, a control well region having a different conductivity type from the inlet well region between the inlet well region and a lower surface of the substrate, a first wiring electrically connecting the first source/drain region and the control well region, and a second wiring electrically connecting the second source/drain region and the inlet well region.