Patent classifications
H10N99/00
Ultrasensitive sensor based on a piezoelectric transistor
Chemical sensors and methods of using and making the same include a functionalized electrode configured to change surface potential in the presence of an analyte. A piezoelectric element is connected to the functionalized electrode and is configured to change in volume in accordance with the surface potential of the functionalized electrode. A piezoresistive element is in contact with the piezoelectric element and is configured to change in resistance in accordance with the volume of the piezoelectric element.
ULTRASENSITIVE SENSOR BASED ON A PIEZOELECTRIC TRANSISTOR
Chemical sensors and methods of using and making the same include a functionalized electrode configured to change surface potential in the presence of an analyte. A piezoelectric element is connected to the functionalized electrode and is configured to change in volume in accordance with the surface potential of the functionalized electrode. A piezoresistive element is in contact with the piezoelectric element and is configured to change in resistance in accordance with the volume of the piezoelectric element.
COUPLED QUANTUM DOTS WITH SELF-ALIGNED GATES
A method for forming a semiconductor structure comprising quantum dots with self-aligned gate structures is disclosed. The method comprises structuring a doped silicon-on-isolator to build a source area, a linear structure extending from the source area having at least two distinct broadened areas, a first and a second gate structure simultaneously by a single lithography process; covering the structures with a blanket oxide layer, forming an opening in the blanket oxide layer at a lateral end of the linear structure, etching back the linear structure and the at least two distinct broadened areas below the blanket oxide until the source area is reached, and filling the hollow template with a semiconductor material different to the silicon such that the at least two broadened areas build quantum dot areas.
Programmable logic integrated circuit, semiconductor device, and characterization method
An object of the present invention is to provide a method for effectively performing characterization for circuit verification by static timing analysis, of a programmable logic integrated circuit including a crossbar switch including a resistance-variable element, and a logic circuit logically configured with the crossbar switch, wherein: the programmable logic integrated circuit is divided into a plurality of leaf cells including a plurality of load circuits including a part of the crossbar switch, and a power supply element input to the crossbar switch; the leaf cell is divided into delay paths each including a base leaf cell and a correction leaf cell; and circuit verification is performed based on a delay information library in which a delay time for the base leaf cell and a correction delay for the correction leaf cell are integrated into a delay time for the leaf cell.
NOVEL COMPOUND SEMICONDUCTOR AND USE THEREOF
A novel compound semiconductor which can be used for a solar cell, a thermoelectric material, or the like, and the use thereof.
Variable resistance device and method for manufacturing same
The forming voltage of a variable resistance device used in a non-volatile memory and the like is decreased, and repetition characteristics are improved. In an element structure in which a metal oxide film is sandwiched between a lower electrode and an upper electrode, an island-shaped/particulate region of amorphous aluminum oxide or aluminum oxycarbide is formed on the metal oxide film. Because an oxide deficiency, serving as the nucleus of a filament for implementing an on/off operation of the variable resistance device, is formed from the beginning under the island-shaped or particulate aluminum oxide or the like, the conventional creation of an oxide deficiency by high-voltage application in the initial period of forming can be eliminated. Such a region can be fabricated using a small number of cycles of an ALD process.
Emitter and method for manufacturing the same
A method for manufacturing an emitter comprises providing a semiconductor substrate having a main surface, the semiconductor substrate comprising a cavity adjacent to the main surface. A portion of the semiconductor substrate arranged between the cavity and the main surface of the semiconductor substrate forms a support structure. The method comprises arranging an emitting element at the support structure, the emitting element being configured to emit a thermal radiation of the emitter, wherein the cavity provides a reduction of a thermal coupling between the emitting element and the semiconductor substrate.
Method and device for storing free atoms, molecules and ions in a contact-less, albeit well-defined near surface arrangement
Surface supported quantum wells with a confined surface state capture and stably confine neutral atoms and molecules in a nanometer precise environment. Depending on the physico-chemical conditions in the capturing process, the degree of occupancy, the temperature of the solid substrate, and/or the history of external stimuli like electromagnetic field pulses, these atoms, molecules or clusters assume unique configurations. The atoms or molecules are able to remain coupled to the quantum-well specific electronic state in the confinement and as such exhibit local and delocalized quantum entanglement. The capturing potential arises from the superposition of Pauli repulsion between the captured object and the quantum well-specific confined electronic state. This occurs within on-surface atomic or supramolecular assemblies or surface supported coordination or covalent networks.
Architectures for quantum information processing
A device for quantum information processing is disclosed herein. According to examples, the device comprises a first plurality of confinement regions for confining spinful charge carriers for use as data qudits. The device further comprises a second plurality of confinement regions for confining spinful charge carriers for use as ancillary qudits, each confinement region of the second plurality of confinement regions couplable to measurement apparatus for measuring an ancillary qudit. The device further comprises a third plurality of confinement regions for confining spinful charge carriers, each confinement region of the third plurality of confinement regions situated between a first confinement region of the first plurality of confinement regions and a second confinement region of the second plurality of confinement regions and for use in mediating interactions between a data qudit of the first confinement region and an ancillary qudit of the second confinement region. The device further comprises one or more charge reservoirs. Each confinement region of the third plurality of confinement regions is couplable to a charge reservoir of the one or more charge reservoirs. Methods for operating a device for quantum information processing, and computer-readable media, are also described herein.
PROGRAMMABLE LOGIC INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE, AND CHARACTERIZATION METHOD
An object of the present invention is to provide a method for effectively performing characterization for circuit verification by static timing analysis, of a programmable logic integrated circuit including a crossbar switch including a resistance-variable element, and a logic circuit logically configured with the crossbar switch, wherein: the programmable logic integrated circuit is divided into a plurality of leaf cells including a plurality of load circuits including a part of the crossbar switch, and a power supply element input to the crossbar switch; the leaf cell is divided into delay paths each including a base leaf cell and a correction leaf cell; and circuit verification is performed based on a delay information library in which a delay time for the base leaf cell and a correction delay for the correction leaf cell are integrated into a delay time for the leaf cell.