Piezoelectric transistors with Schottky contacts and power conversion applications utilizing such piezoelectric transistors are disclosed. A piezoelectric transistor configured in accordance with the inventive concepts disclosed herein may be fabricated to behave as a controllable/switchable active device with an intrinsic anti-parallel diode. Piezoelectric transistors configured in this manner may be utilized in power amplifiers, power converters, as well as in a variety of electronic systems/applications.

The present invention provides a method for manufacturing a secondary cell having a plurality of unit cells 21 that are connected in parallel, including, a step to prepare sheet-shaped unit cells each having a structure that a first electrode layer, a metal oxide semiconductor layer, a charging layer, and a second electrode layer are layered, a step to form a cell sheet by connecting the laminated unit cells in parallel, a step to measure a capacity of the cell sheet, and a step to connect a unit cell for capacity adjustment to the cell sheet in parallel when the capacity is smaller than a specification value.

A phononic transistor can be realized by arranging a row of cantilevered structures with attached magnets, elastically extending upward upon application of a magnetic repulsive force to the magnets. In the extended configuration, the phonons are transmitted from source to drain, while in the flattened configuration the phonons are blocked from transmission. A gate element controls the ON and OFF states of the phononic transistor.

A semiconductor device includes a flip-flop circuit, a control line, a first P-type transistor and a first non-volatile storage element, and a second P-type transistor and a second non-volatile storage element. The flip-flop circuit has a circular structure in which a first inverter circuit, a first connection line including a first node, a second inverter circuit, and a second connection line including a second node are coupled in order. The first P-type transistor and the first non-volatile storage element are coupled together in series between the first node and the control line. The second P-type transistor and the second non-volatile storage element are coupled together in series between the second node and the control line. The non-volatile storage element is a magnetic tunnel junction element including a pinned layer, a tunnel barrier layer, and a free layer arranged in order from a position close to the control line.

A method for manufacturing a secondary cell, the secondary cell including a charging layer that captures electrons by forming energy levels in a band gap by causing a photoexcited structural change in an n-type metal oxide semiconductor coated with an insulating material, includes: a coating step to coat a liquid so as to form a coating film that includes constituents that will form the charging layer; a drying step to dry the coating liquid coated in the coating step; a UV irradiating step to form a UV-irradiated coating film by irradiating the dried coating film obtained through the drying step with ultraviolet light; and a burning step to burn a plurality of the UV-irradiated coating films, after forming the plurality of UV-irradiated coating films by repeating a set plural times, the set including the coating step, the drying step, and the UV irradiating step.

A battery having desired characteristics and a method of charging and discharging a battery are provided. A battery according to an embodiment of the present invention includes: a first electrode layer (6); a second electrode layer (7); and a charging layer (3) including an n-type metal oxide semiconductor and an insulating material, a charge voltage generated between the first electrode layer (6) and the second electrode layer (7) being applied to the charging layer (3). On a surface of the charging layer (3), a region in which the second electrode layer (7) is formed is sandwiched between regions in which the second electrode layer (7) is not formed.

IR emission devices comprising an array of polaritonic IR emitters arranged on a substrate, where the emitters are coupled to a heater configured to provide heat to one or more of the emitters. When the emitters are heated, they produce an infrared emission that can be polarized and whose spectral emission range, emission wavelength, and/or emission linewidth can be tuned by the polaritonic material used to form the elements of the array and/or by the size and/or shape of the emitters. The IR emission can be modulated by the induction of a strain into a ferroelectric, a change in the crystalline phase of a phase change material and/or by quickly applying and dissipating heat applied to the polaritonic nanostructure. The IR emission can be designed to be hidden in the thermal background so that it can be observed only under the appropriate filtering and/or demodulation conditions.

A method for manufacturing an emitter comprises providing a semiconductor substrate having a main surface, the semiconductor substrate comprising a cavity adjacent to the main surface. A portion of the semiconductor substrate arranged between the cavity and the main surface of the semiconductor substrate forms a support structure. The method comprises arranging an emitting element at the support structure, the emitting element being configured to emit a thermal radiation of the emitter, wherein the cavity provides a reduction of a thermal coupling between the emitting element and the semiconductor substrate.

An interconnect structure for on-chip information transfer, and a method for on-chip information transfer. The interconnect structure comprises a source configured for electrically generating plasmons; a detector configured for electrically detecting the generated plasmons; and a plasmonic waveguide coupled between the source and the detector.

Certain aspects relate to systems and techniques for folded optic stereoscopic imaging, wherein a number of folded optic paths each direct a different one of a corresponding number of stereoscopic images toward a portion of a single image sensor. Each folded optic path can include a set of optics including a first light folding surface positioned to receive light propagating from a scene along a first optical axis and redirect the light along a second optical axis, a second light folding surface positioned to redirect the light from the second optical axis to a third optical axis, and lens elements positioned along at least the first and second optical axes and including a first subset having telescopic optical characteristics and a second subset lengthening the optical path length. The sensor can be a three-dimensionally stacked backside illuminated sensor wafer and reconfigurable instruction cell array processing wafer that performs depth processing.