Certain aspects of the present disclosure provide techniques for performing machine learning computations in a compute in memory (CIM) array comprising a plurality of bit cells, including: determining that a sparsity of input data to a machine learning model exceeds an input data sparsity threshold; disabling one or more bit cells in the CIM array based on the sparsity of the input data prior to processing the input data; processing the input data with bit cells not disabled in the CIM array to generate an output value; applying a compensation to the output value based on the sparsity to generate a compensated output value; and outputting the compensated output value.

An electronic device includes a bus driver and circuitry. The bus driver is coupled to a parallel bus including N data lines. The circuitry is configured to receive a data unit for transmission over the N data lines, to determine a first count indicative of a number of data bits in the data unit having a predefined value, and a second count indicative of a number of inverted data bits relative to corresponding bits in a previously transmitted data unit, to make a decision of whether to invert the data unit based on the first and second counts, depending on whether such inversion is expected to reduce power consumption of transmitting the data unit over the bus, to produce an output data unit by retaining or inverting the data unit based on the decision, and to transmit the output data unit over the data lines via the bus driver.

An immersion cooling assembly comprises at least one primary heat-generating electronic component and a flow-through cooling module mounted near the at least one primary heat-generating component. The flow-through cooling module comprises at least one inlet conduit to accept an inflow of pressurized dielectric coolant, a fluid chamber through which fluid flows to provide targeted, direct cooling to a heat-generating component, and exit passageways to facilitate flow-through of the dielectric coolant into a surrounding immersion bath for cooling of other components. As it flows out of the cooling module and over the heat-generating component, the coolant fluid absorbs heat from the heat-generating electronic component. In certain embodiments, the assembly may also comprise at least one periphery heat-generating electronic component, which may also be cooled by the dielectric coolant as it exits the vicinity of the flow-through cooling module. The cooling module may include impingement nozzles to accelerate and direct the flow of coolant fluid toward the high-heat-generating electronic component.

A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

The present invention discloses a method for external devices accessing computer memory, which includes: the external device applying to a computer for a memory space with a certain size, and receiving multiple memory blocks fed back by the computer; the external device establishing a memory mapping relation between the external device and the computer by means of a sequential storage structure or a chain storage structure; and when initiating a read-and-write operation, the external device finding the corresponding offset address in said computer according to the memory mapping relation between the external device and the computer, generating a read-and-write burst command, and actualizing read-and-write operations in the computer memory. The present invention can achieve the rapid and continuous access to multiple discontinuous memory areas of the computer memory, and improve the speed in the computer’s operating system and external devices accessing the memory.

A memory module is provided. The memory module includes: a control chip, at least one data flash memory chip, at least two memory cells, and at least one non-volatile memory, each of the at least one data flash memory chip is connected to at least one of the at least two memory cells and at least one of the at least one non-volatile memory, the control chip is connected to the at least one data flash memory chip and the at least two memory cells, and the memory is further connected to at least one capacitor; the control chip is configured to send a control command; and each of the at least one data flash memory chip is configured to perform, based on the control command from the control chip, data processing between the memory cell connected thereto and the non-volatile memory connected thereto.

A method of circuit conception of a computational memory circuit including a memory having memory cells, the method including: receiving an indication of the memory storage size and an indication of an instruction frequency of the instructions to be executed by the computational memory circuit; evaluating for a plurality of candidate types of memory cells, a number representing an average number of cycles of the memory of the computational memory circuit per instruction to be executed; determining, for each of the plurality of candidate types of memory cells, a minimum operating frequency of the computational memory circuit based on the number N and on the memory storage size; selecting one of the plurality of candidate types of memory cells based on the determined minimum operating frequency; and performing the circuit conception based on the selected type of candidate memory cell.

A computer-implemented method comprises generating computer executable code as one or more code portions; detecting a number of processing operations required to reach one or more predetermined stages in execution of each code portion; and associating with each code portion one or more progress indicators, each representing a respective execution stage of the one or more predetermined stages within execution of that code portion. The code portions are executed by a processor powered by an unpredictable power source. When the processor detects an energy condition indicating that no more than a reserve quantity of electrical energy is available, the progress indicators are used to determine whether or not to perform a checkpoint.

The disclosure relates to method and apparatus for operating image data. The method includes: reading matrix data from the image data based on a matrix size, M rows and N columns, of an image operator (220); calculating column data in the matrix data with a single calculation instruction corresponding to the image operator, to obtain an intermediate calculation result (240); multiplexing and rearranging the intermediate calculation result into N rows of cached data (260); calculating matrix elements of a target column in the N rows of cached data with the single calculation instruction, to obtain a calculation result of the matrix data under the single calculation instruction (280); and outputting the calculation result as an image processing result of the matrix data by the image operator (300).

A semiconductor device that has low power consumption and is capable of performing arithmetic operation is provided. The semiconductor device includes first to third circuits and first and second cells. The first cell includes a first transistor, and the second cell includes a second transistor. The first and second transistors operate in a subthreshold region. The first cell is electrically connected to the first circuit, the first cell is electrically connected to the second and third circuits, and the second cell is electrically connected to the second and third circuits. The first cell sets current flowing from the first circuit to the first transistor to a first current, and the second cell sets current flowing from the second circuit to the second transistor to a second current. At this time, a potential corresponding to the second current is input to the first cell. Then, a sensor included in the third circuit supplies a third current to change a potential of the second wiring, whereby the first cell outputs a fourth current corresponding to the first current and the amount of change in the potential.