Systems and methods of adaptive thermal control are provided for information handling system platforms that may be implemented to automate and scale fan control settings by making the fan control settings relative to a reported component thermal control parameter value from a component of an information handling system platform, such as a CPU or other heat generating component. In one example, bounds for system use of vendor or component manufacturer-reported thermal control parameter values may be set for system cooling so as to confine use of these values within information handling system platform limits characterized by a manufacturer of an information handling system platform.

Power consumption of a cooling fan of an information processing device is reduced. A processor reduces a speed of the cooling fan provided in the information processing device, and controls the cooling fan at a first speed when there is no problem with the operation of the information processing device, the first speed being obtained by reducing the speed of the cooling fan. An interface transmits first information indicating the first speed to a management device. The processor receives second information indicating a second speed from the management device that associates the first speed with identification information identifying the information processing device and stores therein the first information indicating the first speed and the identification information, and controls the speed of the cooling fan according to the second speed when the second speed is lower than the first speed.

A computer system including a PCH (platform controller hub), a CPLD (complex programmable logic device), a first switch and a processor, and a control method are provided to control the operation frequency of the processor. The CPLD is coupled to the PCH and the first switch. The processor is coupled to the first switch. The PCH produces and outputs a second control signal according to the first firmware and a first control signal from a command input unit. The CPLD produces and outputs a third control signal according to the second firmware and the second control signal. The first switch receives the third control signal and is turned on to output a triggering signal when the third control signal is valid. The processor includes a PROCHOT pin. The processor receives the triggering signal and triggers the PROCHOT pin for frequency control.

According to some examples, systems and methods are provided for determining a set of power states supported by a data storage device and applying an operation to the data storage device based on whether the set of power states includes a low power state.

An apparatus is described. The apparatus can include non-volatile memory, an embedded processor, and a memory controller. The memory controller can access data from the byte addressable non-volatile memory using at least one of: a first addressing scheme or a second addressing scheme. The memory controller can provide the data to a host system over a first interface when the data is accessed using the first addressing scheme. The memory controller can provide the data to the embedded processor over a second interface when the data is accessed using the second addressing scheme.

Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2.sup.n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.

Information apparatus and application software supporting printing over air or network are herein disclosed and enabled. The information apparatus may include one or more software components that include (1) a discovery component to discover a supported printer in a local area network (LAN) and to receive device information related to the printer (e.g., capability, language or format supported, identification) from the printer, and (2) a printing component to generate or obtain print data based on the device information received and to transmit the print data to the discovered printer. After establishing the connection to the LAN, application software (e.g., Internet browser, email, photos, documents) in the information apparatus may print digital content by using the discovery component to discover the printer in the LAN, and may use the printing component to obtain and transmit print data in a form that is acceptable to the printer for printing the digital content.

A host device can download a firmware update to a peripheral device having previously enumerated with the host device. The host device can perform link training with the peripheral device in response to a re-enumeration indication received from the peripheral device. The link training can include switching a Link Training and Status State Machine (LTSSM) in the host device from an active state (U0) to an RX.Detect state and synchronizing with the peripheral device in the RX.Detect state. The host device can re-enumerate with the peripheral device utilizing the firmware update after the host device completes link training with the peripheral device.

In various embodiments, apparatuses and methods are disclosed to keep a memory clock gated when the data for a current memory address is the same as the data in the immediate previous memory address. For a write function, new data will only be written into the current memory address if it is different from the data in the immediate previous memory address. Similarly, for a read function, the data will only be read out of the current memory address if it is different from the data in the immediate previous memory address. Each row in the memory may have one associated status bit outside the memory. Data may only be written to or read from the current memory address when the status bit is set. Clock gating the memory ports may reduce the overall power consumption of the memory.

Disclosed is an electronic device including a touch sensor configured to sense at least one touch on at least two different lateral sides of the electronic device, and a controller configured to determine a state of the electronic device when the electronic device has been gripped, determine a grip pattern based on the sensed at least one touch on the at least two different lateral sides of the electronic device, and perform a function based on the determined grip pattern and state of the electronic device.