Examples of methods for controlling machine learning model structures are described herein. In some examples, a method includes controlling a machine learning model structure. In some examples, the machine learning model structure may be controlled based on an environmental condition. In some examples, the machine learning model structure may be controlled to control apparatus power consumption associated with a processing load of the machine learning model structure.

Methods and systems relating to improved processing architectures with pre-staged instructions are disclosed herein. A disclosed processor includes an instruction memory, at least one functional processing unit, a bus, a set of instruction registers configured to be loaded, using the bus, with a set of pre-staged instructions from the instruction memory, and a logic circuit configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.

Various embodiments include methods and systems for providing sleep clock edge-based global counter synchronization in a multiple-chiplet system. A system-on-a-chip (SoC) may include a first chiplet including a first chiplet global counter subsystem, and a second chiplet including a second chiplet global counter subsystem. The SoC may further include an interface bus communicatively coupling the first chiplet and the second chiplet, and a power management integrated circuit (PMIC) configured to supply a sleep clock to the first chiplet and the second chiplet. The first chiplet may be configured to transmit a global counter synchronization pulse trigger to the second chiplet across the interface bus. The second chiplet may be configured to load a global counter synchronization value into the second chiplet global counter subsystem at a sleep clock synchronization edge of the sleep clock in response to receiving the global counter synchronization pulse trigger.

Methods and apparatus for performing machine learning tasks, and in particular, to a neural-network-processing architecture and circuits for improved handling of partial accumulation results in weight-stationary operations, such as operations occurring in compute-in-memory (CIM) processing elements (PEs). One example PE circuit for machine learning generally includes an accumulator circuit, a flip-flop array having an input coupled to an output of the accumulator circuit, a write register, and a first multiplexer having a first input coupled to an output of the write register, having a second input coupled to an output of the flip-flop array, and having an output coupled to a first input of the first accumulator circuit.

A method for deploying bare computers implemented in an electronic device includes starting at least one bare computer to be deployed, and assigning an IP address to the at least one bare computer; downloading a deployment image to the at least one bare computer based on the IP address, and obtaining hardware information of the at least one bare computer based on the deployment image; determining at least one service to be provided by the bare computer according to a preset deployment strategy and the obtained hardware information of the bare computer; and generating a system image according to the at least one service to be provided by the bare computer, and deploying the system image in the bare computer.

Embodiments described herein are generally directed to improving predictions regarding workload performance to facilitate dynamic auto device selection. In an example, based on telemetry samples collected from a computer system in real-time and indicative of a state of the computer system, one or more workload performance prediction models are built or updated for a heterogeneous set of computer resources of the computer system with reference to one or more optimization goals. At a time of execution of a workload, a particular computer resource of the heterogeneous set of computer resources on which to dispatch the workload is dynamically determined by: (i) generating multiple predicted performance scores each corresponding to one of the computer resources based on the state of the computer system and the one or more workload performance prediction models; and (ii) selecting the particular computer resource based on the predicted performance scores.

A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

A method for providing more than one function to pins of a programmable device used in a server system includes the programmable device and first and second devices. The programmable device is electrically connected to the first device and the second device. The programmable device includes a major logic communication device, a detection module, a storage module, and at least one multiplexing pin. The second device is powered on, sending an in-position signal to the detection module through the at least one multiplexing pin. The detection module transmits the in-position signal to the storage module. The major logic communication module communicates with the first device through the at least one multiplexing pin. A system applying the method are also disclosed.

The disclosed computing device may include electronic components, at least one of which is a processor. The computing device may also include a heat sink thermally coupled to the electronic components, as well as a temperature sensor that determines the current temperature inside the computing device. The computing device may further include a controller. The processor may generate a load schedule for the electronic components based on the current temperature inside the computing device. This load schedule ensures that a maximum temperature for the heat sink is not exceeded even when the total system power load exceeds, for a short period of time, the maximum sustainable power level the heat sink can dissipate. The controller may then load the electronic components according to the generated load schedule. Various other methods, systems, and computer-readable media are also disclosed.

A machine learning model is trained for user activity detection and context detection on a mobile device. The machine learning model is configured to learn a statistical relationship between an always-on sensing modality of the mobile device and actual user context. Rather than user annotations, the machine learning model is enhanced and personalized for the always-on sensing modality by automated annotations obtained from non-always-on sensing modalities. The non-always-on sensing modality opportunistically provides an imperfect label of user context, where the imperfect label has a known associated probability of error.