Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

An apparatus and method for providing ML processing for one or more ML applications operating on one or more Internet of Things (IoT) devices includes receiving a ML request from an IoT device. The ML request can be generated by a ML application operating on the IoT device and include input data collected by the first ML application. A ML model to perform ML processing of the input data included in the ML request is identified and provided to an ML core for ML processing along with the input data included in the first ML request. The ML core produces ML processing output data based on ML processing by the ML core of input data included in the ML request using the ML model. The ML processing output data can be transmitted to the IoT device.

A memory module may include: a battery; a plurality of devices including a first memory, a second memory, and a controller; and a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices.

A system is described that turns off a high power, power supply when a device no longer needs high power. A low power, power supply or a rechargeable battery provides power to determine when the device again needs high power. The low power supply consumes a minimum possible power when the device does not need high power and the power rechargeable battery is not charged. That is, the high power and low power, power supplies are turned on or off based on the real time power consumption need of the device and the charged state of the battery. The power need of the device is monitored by a current shunt monitoring circuit and a control signal monitoring circuit.

Techniques for optimizing CPU usage in a host system based on VM guest OS power and performance management are provided. In one embodiment, a hypervisor of the host system can capture information from a VM guest OS that pertains to a target power or performance state set by the guest OS for a vCPU of the VM. The hypervisor can then perform, based on the captured information, one or more actions that align usage of host CPU resources by the vCPU with the target power or performance state.

A compilation system can define, at compile time, the data blocks to be managed by an Even Driven Task (EDT) based runtime/platform, and can also guide the runtime/platform on when to create and/or destroy the data blocks, so as to improve the performance of the runtime/platform. The compilation system can also guide, at compile time, how different tasks may access the data blocks they need in a manner that can improve performance of the tasks.

Eyewear including a support structure defining a region for receiving a head of a user. The support structure supports optical elements, electronic components, and a use detector. The use detector is coupled to the electronic components and is positioned to identify when the head of the user is within the region defined by the support structure. The electronic components monitor the use detector and transition from a first mode of operation to a second mode of operation when the use detector senses the head of the user in the region.

The present application relates to a semiconductor memory training method and related devices, belonging to the technical field of semiconductors. The method comprises: obtaining a stored historical training result of a semiconductor memory, the historical training result comprising a historical expected delay value and a historical expected voltage; setting a delay threshold and a current training voltage range, the delay threshold being less than or equal to the historical expected delay value, the current training voltage range comprising the historical expected voltage; obtaining a current minimum delay value for the semiconductor memory under the historical expected voltage; and using the stored historical training result as a current training result of the semiconductor memory, if the current minimum delay value for the semiconductor memory under the historical expected voltage is no less than the delay threshold.

An information processing apparatus that detects a voice command via a microphone in order to activate the device and execute certain applications. The apparatus comprises a digital signal processor (DSP) and a host controller which are responsible for processing the voice commands. The DSP recognizes and processes voice commands intermittently while the host processor is in a sleep state, thereby reducing the overall power consumption of the apparatus. Further, when the DSP is configured to recognize voice commands intended, only to activate the device, a memory having a sufficiently lower storage capacity suffices.

An apparatus 2 has a processing pipeline 4 supporting at least a first processing mode and a second processing mode with different energy consumption or performance characteristics. A storage structure 22, 30, 36, 50, 40, 64, 44 is accessible in both the first and second processing modes. When the second processing mode is selected, control circuitry 70 triggers a subset 102 of the entries of the storage structure to be placed in a power saving state.