An embodiment of the present disclosure provides an operation apparatus which includes a storage unit, a control unit and a compute unit. The technical solution provided in this disclosure can reduce resource consumption of convolution operation, improve the speed of convolution operation and reduce operation time.

An automatic power on apparatus, system, method, and circuit automatically control the on/off state of a first electronic device or a second electronic device. When the second electronic device is positioned on, in, or proximate to the mounting area of the first electronic device, the automatic power on circuit establishes a coupling signal between a first portion of the automatic power on circuit and a second portion of the automatic power on circuit, activates the automatic power on circuit based on the coupling signal, and automatically controls an on/off state of the first electronic device or the second electronic device based on the activation of the automatic power on circuit.

To provide a semiconductor device with a novel structure. The semiconductor device includes an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. Each of the first transistor and the second transistor includes a semiconductor layer including a metal oxide in a channel formation region. The arithmetic circuit includes a third transistor. The third transistor includes a semiconductor layer including silicon in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer including the first transistor is provided over a layer including the third transistor. The layer including the second transistor is provided over the layer including the first transistor. The data retention characteristics of the first memory circuit are different from those of the second memory circuit.

An unnecessary circuit operation in a clock enabler circuit accompanying toggling of a clock signal is suppressed. A state holding unit performs a holding operation of a state as to whether or not to output an output clock signal according to an internal clock signal. A clock signal output unit controls output of the output clock signal according to the state held in the state holding unit. A control unit supplies, to the state holding unit, the internal clock signal and a value of the state that are necessary for the holding operation in the state holding unit on a basis of a clock signal and a clock enable signal from an outside.

A blockchain-based interaction method and system for an edge computing service: using, as a bearing entity of an MECaaS, a device that has an environment for an operating system and that is of a user; registering a computing power device of the user as an edge node by using the MECaaS; uploading or updating registration information of the edge node to a blockchain layer; issuing, by a requesting device as a data producer, a computing task to the MECaaS; invoking, by the MECaaS, the smart contract deployed on the blockchain layer; standardizing a data format of the computing task; matching a target edge node for the requesting device; establishing an M2M communication between the requesting device and the target edge node, so that the requesting device can transmit raw data to the target edge node, and the target edge node can feed back a computing result to the requesting device.

A method is provided for obtaining display data. The method includes: obtaining rendering data corresponding to an application program surface; obtaining, in response to detecting an operation of adjusting a dimension of the application program surface, a transformation coefficient corresponding to the application program surface, where the transformation coefficient is a scale value between a dimension of the application program surface after adjustment and a dimension before adjustment; and obtaining display data of a corresponding masking layer of the application program surface according to the transformation coefficient and the rendering data.

A data fabric routes requests between the plurality of requestors and the plurality of responders. The data fabric includes a crossbar router, a coherent slave controller coupled to the crossbar router, and a probe filter coupled to the coherent slave controller and tracking the state of cached lines of memory. Power state control circuitry operates, responsive to detecting any of a plurality of designated conditions, to cause the probe filter to enter a retention low power state in which a clock signal to the probe filter is gated while power is maintained to the probe filter. Entering the retention low power state is performed when all in-process probe filter lookups are complete.

PAM encoding techniques that leverage unused idle periods in channels between data transmissions to apply longer but more energy-efficient codes. To improve energy savings, multiple sparse encoding schemes may be utilized selectively to fit different sized gaps in the traffic. These approaches may provide energy reductions, for example with memory READ and WRITE traffic, when transferring 4-bit data using 3-symbol sequences.

A computer may be provided on a mining machine comprising a mother board, a power supply in operable communication with the mother board, an input/output interface in communication with the mother board, and a plurality of hash boards each in communication with the mother board and comprising a plurality of mining chips. The computer may execute instructions that cause the computer to perform establishing communication with an external device, retrieving at least one profit variable from the external device, calculating an estimated profitability of a first mining chip based on the profit variable, and adjusting a chip voltage supplied to the first mining chip and adjusting a chip frequency of the first mining chip to maximize the estimated profitability. Alternatively, the instructions may cause the computer to adjust the chip voltage and the chip frequency to maintain a temperature within a predetermined range.

A cooling mechanism apparatus, system, and method for adaptively controlling heat of a vehicle processor, includes a processor configured to control deactivation or activation of an application driving the in-vehicle controller depending on grades of a predetermined functional safety level of the application and to determine an order of the deactivation or the activation of the application when heat is generated in the controller.