Patent classifications
B81C3/00
MEMS DEVICE AND PROCESS
The application describes MEMS transducer structures comprising a membrane structure having a flexible membrane layer and at least one electrode layer. The electrode layer is spaced from the flexible membrane layer such that at least one air volume extends between the material of the electrode layer and the membrane layer. The electrode layer is supported relative to the flexible membrane by means of a support structure which extends between the first electrode layer and the flexible membrane layer.
Light module
A light module includes an optical element and a base on which the optical element is mounted. The optical element has an optical portion which has an optical surface; an elastic portion which is provided around the optical portion such that an annular region is formed; and a pair of support portions which is provided such that the optical portion is sandwiched in a first direction along the optical surface and in which an elastic force is applied and a distance therebetween is able to be changed in accordance with elastic deformation of the elastic portion. The base has a main surface, and a mounting region in which an opening communicating with the main surface is provided. The support portions are inserted into the opening in a state where an elastic force of the elastic portion is applied.
Microfluidic device capable of removing microbubbles in channel by using porous thin film, sample injection device for preventing inflow of bubbles, and method for bonding panel of microfluidic element by using mold-releasing film
Provided is a microfluidic device capable of removing microbubbles in a channel by using a porous thin film, the microfluidic device comprising: an upper panel comprising a microfluidic channel through which a fluid passes; a porous thin film attached to the bottom surface of the microfluidic channel so as to remove microbubbles included in the fluid that passes through the microfluidic channel; a lower panel contacting the bottom surface of the porous thin film and the upper panel, a path being provided in the lower panel so as to discharge microbubbles, which pass through the porous thin film, to the outside; and a vacuum-suctioning means for vacuum-suctioning the upper panel and the lower panel such that the microfluidic channel, to which the porous thin film is attached, is attached to the lower panel in a vacuum state.
MICROCHANNEL CHIP AND METHOD FOR MANUFACTURING SAME
A microchannel chip with which channel deformation does not occur even when high-temperature and high-pressure sterilization treatment is performed and with which strong joining performance of substrates is maintained; and a method for manufacturing the same are provided. A microchannel chip comprising: a channel substrate having a microchannel formed on at least one surface thereof; a lid substrate; and a joining layer joining the channel substrate and the lid substrate, wherein the channel substrate, the lid substrate, and the joining layer are each formed of a cycloolefin polymer, a glass-transition temperature Tg.sub.s1 of a cycloolefin polymer forming the channel substrate, a glass-transition temperature Tg.sub.s2 of a cycloolefin polymer forming the lid substrate, and a glass-transition temperature Tg.sub.2 of a cycloolefin polymer forming the joining layer have relationships: Tg.sub.s1>Tg.sub.2; and Tg.sub.s2>Tg.sub.2, and the joining layer has a thickness within a specific range.
Microchip
Provided is a microchip that can achieve a favorable bonding state in the bonding portion between first and second substrates even if the microchip is large in size. A microchip includes a first substrate made of a resin and a second substrate made of a resin, the first substrate and the second substrates being bonded to each other, and a channel surrounded by a bonding portion between the first substrate and the second substrate is formed by a channel forming step formed at least in the first substrate. Further, a noncontact portion is formed to surround the bonding portion, and an angle θ.sub.1 formed between a side wall surface of the channel forming step and a bonding surface continuous therewith satisfies θ.sub.1>90°.
Power electronics assemblies with CIO bonding layers and double sided cooling, and vehicles incorporating the same
A 2-in-1 power electronics assembly includes a frame with a lower dielectric layer, an upper dielectric layer spaced apart from the lower dielectric layer, and a sidewall disposed between and coupled to the lower dielectric layer and the upper dielectric layer. The lower dielectric layer includes a lower cooling fluid inlet and the upper dielectric layer includes an upper cooling fluid outlet. A first semiconductor device assembly and a second semiconductor device assembly are included and disposed within the frame. The first semiconductor device is disposed between a first lower metal inverse opal (MIO) layer and a first upper MIO layer, and the second semiconductor device is disposed between a second lower MIO layer and a second upper MIO layer. An internal cooling structure that includes the MIO layers provides double sided cooling for the first semiconductor device and the second semiconductor device.
Hybrid ultrasonic transducer and method of forming the same
A method of manufacturing a semiconductor device includes: forming a first substrate includes a membrane stack over a first dielectric layer, the membrane stack having a first electrode, a second electrode over the first electrode and a piezoelectric layer between the first electrode and the second electrode, a third electrode over the first dielectric layer, and a second dielectric layer over the membrane stack and the third electrode; forming a second substrate, including: a redistribution layer (RDL) over a third substrate, the RDL having a fourth electrode; and a first cavity on a surface of the RDL adjacent to the fourth electrode; forming a second cavity in one of the first substrate and the second substrate; and bonding the first substrate to the second substrate.
Micro-electromechanical (MEM) power relay
A micro-electromechanical (MEM) relay and its fabrication process. The MEM relay includes a movable actuator electrode anchored to a substrate with two cantilever beams. Below the actuator electrode, there are three fixed electrodes. These three electrodes are the gate, the input, and the output contacts. The square base of the actuator electrode, and the square gate electrode below it, form an electrostatic parallel-plate actuator. When a voltage is applied between the actuator electrode and the gate electrode, the actuator electrode is pulled-down due to electrostatic attraction closing the relay. When the voltage is removed, the cantilever beams act as springs opening the relay.
Attachment method for microfluidic device
A microfluidic device includes a silicon device and a metallic component. The silicon device and the metallic component are attached by preparing a surface of a silicon device to be solderable, preparing a corresponding surface of a metallic component to be solderable, and soldering the prepared surface of the silicon device to the corresponding prepared surface of the metallic component with a solder of a pre-defined composition and thickness to accommodate strain due to co-efficient of thermal expansion (CTE) mismatch between the silicon device and the metallic component.
PARTIAL DICING PROCESS FOR WAFER-LEVEL PACKAGING
An encapsulation chip manufacturing method includes forming first and second dicing grooves in a surface of a cap wafer and aligning the cap wafer and a device substrate such that the surface of the cap wafer faces a surface of the device substrate. The device substrate includes a device affixed to the surface and a bond pad on the surface and coupled to the device. The cap wafer is bonded to the device substrate and partially diced at the first and second dicing grooves such that the bond pad is exposed. Aligning the cap wafer and the device substrate includes aligning the first and second dicing grooves between the bond pad and a bonding area at which the cap wafer is bonded to the device substrate. A width of the first and second dicing grooves prevents cap wafer dust formed during the partial dicing from falling on the bond pad.