Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a substrate; a multilayer stack of reflective layers on the substrate; a capping layer on the multilayer stack of reflecting layers; an absorber layer on the capping layer, the absorber layer comprising an antimony-containing material; and a hard mask layer on the absorber layer, the hard mask layer comprising a hard mask material selected from the group consisting of CrO, CrON, TaNi, TaRu and TaCu.

A semiconductor device includes a semiconductor chip made of a SiC substrate and having main electrodes on one surface and a rear surface, first and second heat sinks, respectively, disposed adjacent to the one surface and the rear surface, a terminal member interposed between the second heat sink and the semiconductor chip, and a plurality of bonding members disposed between the main electrodes, the first and second heat sinks, and the terminal member. The terminal member includes plural types of metal layers symmetrically layered in the plate thickness direction. The terminal member as a whole has a coefficient of linear expansion at least in a direction orthogonal to the plate thickness direction in a range larger than that of the semiconductor chip and smaller than that of the second heat sink.

A semiconductor device includes a semiconductor chip made of a SiC substrate and having main electrodes on one surface and a rear surface, first and second heat sinks, respectively, disposed adjacent to the one surface and the rear surface, a terminal member interposed between the second heat sink and the semiconductor chip, and a plurality of bonding members disposed between the main electrodes, the first and second heat sinks, and the terminal member. The terminal member includes plural types of metal layers symmetrically layered in the plate thickness direction. The terminal member as a whole has a coefficient of linear expansion at least in a direction orthogonal to the plate thickness direction in a range larger than that of the semiconductor chip and smaller than that of the second heat sink.

A sliding member including an overlay capable of realizing good fatigue resistance while preventing interlayer peeling. The sliding member including an overlay formed of an alloy plating film of Bi and Sb, wherein Bi—Sb oxide is formed on a surface of the overlay.

A sliding member including an overlay capable of realizing good fatigue resistance while preventing interlayer peeling. The sliding member including an overlay formed of an alloy plating film of Bi and Sb, wherein Bi—Sb oxide is formed on a surface of the overlay.

A solder paste includes a first solder alloy powder in an amount ranging from 30% to 95% by weight. The first solder alloy powder includes a first solder alloy with a solidus temperature of 200° C. to 260° C. The first solder alloy includes an Sn—Cu alloy or an Sn—Cu—Ag alloy. The solder paste further includes a second solder alloy powder in an amount ranging from 5% to 70% by weight, and a solder flux. The second solder alloy powder includes a second solder alloy with a solidus temperature below 250° C. The solder paste has a variable melting point. In multiple reflow soldering, a remelting of the solder paste is inhibited under different temperature conditions so that no functional failure occurs during assembly and/or packaging of PCBs or electronic devices due to melting of solder.

A solder paste includes a first solder alloy powder in an amount ranging from 30% to 95% by weight. The first solder alloy powder includes a first solder alloy with a solidus temperature of 200° C. to 260° C. The first solder alloy includes an Sn—Cu alloy or an Sn—Cu—Ag alloy. The solder paste further includes a second solder alloy powder in an amount ranging from 5% to 70% by weight, and a solder flux. The second solder alloy powder includes a second solder alloy with a solidus temperature below 250° C. The solder paste has a variable melting point. In multiple reflow soldering, a remelting of the solder paste is inhibited under different temperature conditions so that no functional failure occurs during assembly and/or packaging of PCBs or electronic devices due to melting of solder.

Provided are a Sn—Bi—In-based low melting-point joining member used in a Pb-free electroconductive joining method in mounting a semiconductor component, and is usable for low-temperature joining, and a manufacturing method therefor.

A Sn—Bi—In-based low melting-point joining member, including a Sn—Bi—In alloy that has a composition within a range represented by a quadrangle in a Sn—Bi—In ternary phase diagram, a first quadrangle having four vertices including: Point 1 (1, 69, 30), Point 2 (26, 52, 22), Point 3 (40, 10, 50), and Point 4 (1, 25, 74), where Point (x, y, z) is defined as a point of x mass % Sn, y mass % Bi and z mass % In, and that also has a melting point of 60 to 110° C. As well as a method for producing a Sn—Bi—In-based low melting-point joining member, including a plating step of forming a plated laminate on an object to be plated, the plated laminate including a laminated plating layer obtained by performing Sn plating, Bi plating, and In plating respectively such that the laminated plating layer has a composition within the range represented by the first quadrangle.

Some implementations of the disclosure are directed to low melting temperature (e.g., liquidus temperature below 210° C.) SnIn solder alloys. A SnIn solder alloy may consist of: 8 to 20 wt % In; greater than 0 wt % to 4 wt % Ag; optionally, one or more of greater than 0 wt % to 5 wt % Sb, greater than 0 wt % to 3 wt % Cu, greater than 0 wt % to 2.5 wt % Zn, greater than 0 wt % to 1.5 wt % Ni, greater than 0 wt % to 1.5 wt % Co, greater than 0 wt % to 1.5 wt % Ge, greater than 0 wt % to 1.5 wt % P, and greater than 0 wt % to 1.5 wt % Mn; and a remainder of Sn.

Some implementations of the disclosure are directed to low melting temperature (e.g., liquidus temperature below 210° C.) SnIn solder alloys. A SnIn solder alloy may consist of: 8 to 20 wt % In; greater than 0 wt % to 4 wt % Ag; optionally, one or more of greater than 0 wt % to 5 wt % Sb, greater than 0 wt % to 3 wt % Cu, greater than 0 wt % to 2.5 wt % Zn, greater than 0 wt % to 1.5 wt % Ni, greater than 0 wt % to 1.5 wt % Co, greater than 0 wt % to 1.5 wt % Ge, greater than 0 wt % to 1.5 wt % P, and greater than 0 wt % to 1.5 wt % Mn; and a remainder of Sn.