Patent classifications
G01R11/00
Dynamic OCP adjustment
An example computing system may include computer module bays, a power subsystem to supply power to computer modules installed in the computer module bays, and a system controller. The power subsystem may also implement overcurrent protection (OCP) based on an OCP threshold parameter. The system controller may include dynamic OCP adjustment logic that repeatedly updates the OCP threshold parameter during normal operation of the computing system. The dynamic OCP adjustment logic may update the OCP threshold parameter by determining a power requirement of the computing system based on a current configuration of the computing system, determining a new OCP threshold based on the power requirement, and instructing the power subsystem to change a value of the OCP threshold parameter to a new value based on the new OCP threshold.
Dynamic OCP adjustment
An example computing system may include computer module bays, a power subsystem to supply power to computer modules installed in the computer module bays, and a system controller. The power subsystem may also implement overcurrent protection (OCP) based on an OCP threshold parameter. The system controller may include dynamic OCP adjustment logic that repeatedly updates the OCP threshold parameter during normal operation of the computing system. The dynamic OCP adjustment logic may update the OCP threshold parameter by determining a power requirement of the computing system based on a current configuration of the computing system, determining a new OCP threshold based on the power requirement, and instructing the power subsystem to change a value of the OCP threshold parameter to a new value based on the new OCP threshold.
Power metering transducer system
Devices, methods, systems, and computer-readable media for power metering are described herein. One or more embodiments include a power metering device, comprising a number of sensors configured to output pulses corresponding to a quantity of power consumed over a period of time, a first module configured to receive the pulses from the number of sensors, and meter power consumption using the output pulses. In addition the power metering device includes a second module configured to communicate with the number of sensors using a plurality of communication protocols.
METHOD AND SYSTEM FOR PROVIDING SOUND DATA FOR GENERATION OF AUDIBLE NOTIFICATION RELATING TO POWER CONSUMPTION
A method and a system (110) for providing sound data for generation of an audible notification relating to power consumption at a site (120) are disclosed. The system receives (201) information about power consumption at the site (120); and The system determines (202) the sound data based on the information about power consumption and on preference of a user of the system (110). A corresponding computer program and a carrier therefor are also disclosed.
Semiconductor integrated circuit, circuit designing apparatus, and circuit designing method
According to one embodiment, a semiconductor integrated circuit includes: a logic circuit including a first scan chain configured to operate based on a first clock signal and a second scan chain configured to operate based on a second clock signal in a built-in self-test; a pattern generator configured to generate a test pattern and transmit the test pattern to the first and second scan chains; a compression circuit configured to compress first data received from the first and second scan chains; a clock select circuit configured to select one of the first and second clock signals and transmit the one of the first and second clock signals to the corresponding one of the first and second scan chains in the test; and a test control circuit configured to control the test and detect a fault in the logic circuit based on a result of the test.
Semiconductor integrated circuit, circuit designing apparatus, and circuit designing method
According to one embodiment, a semiconductor integrated circuit includes: a logic circuit including a first scan chain configured to operate based on a first clock signal and a second scan chain configured to operate based on a second clock signal in a built-in self-test; a pattern generator configured to generate a test pattern and transmit the test pattern to the first and second scan chains; a compression circuit configured to compress first data received from the first and second scan chains; a clock select circuit configured to select one of the first and second clock signals and transmit the one of the first and second clock signals to the corresponding one of the first and second scan chains in the test; and a test control circuit configured to control the test and detect a fault in the logic circuit based on a result of the test.
Magnetic position sensor system, device, magnet and method
A position sensor system for determining a position of a sensor device relative to a magnetic structure, the system comprising: said magnetic structure comprising a plurality of non-equidistant poles; said sensor device comprising at least three magnetic sensors spaced apart over predefined distances; and the sensor device being adapted for: a) measuring at least three in-plane magnetic field components, and for calculating two in-plane field gradients therefrom; b) measuring at least three out-of-plane magnetic field components, and for calculating two out-of-plane field gradients therefrom; c) calculating a coarse signal based on these gradients; d) calculating a fine signal based on these gradients; e) determining said position based on the coarse signal and the fine signal.
Systems and methods for automated elevator component inspection
Methods and systems for automatically checking an operational status of electrical components of an elevator system, the methods including setting a first power state of all addressed electrical components of the elevator system, measuring a control value power consumption with a power consumption counter, switching a first addressed electrical component into a second power state, monitoring a power consumption associated with the first addressed electrical component, comparing the power consumption associated with the first addressed electrical component with the control value power consumption, and when the power consumption associated with the first addressed electrical component is not greater than the control value power consumption, performing a detected failure operation.
Systems and methods for automated elevator component inspection
Methods and systems for automatically checking an operational status of electrical components of an elevator system, the methods including setting a first power state of all addressed electrical components of the elevator system, measuring a control value power consumption with a power consumption counter, switching a first addressed electrical component into a second power state, monitoring a power consumption associated with the first addressed electrical component, comparing the power consumption associated with the first addressed electrical component with the control value power consumption, and when the power consumption associated with the first addressed electrical component is not greater than the control value power consumption, performing a detected failure operation.
SEMICONDUCTOR INTEGRATED CIRCUIT, CIRCUIT DESIGNING APPARATUS, AND CIRCUIT DESIGNING METHOD
According to one embodiment, a semiconductor integrated circuit includes: a logic circuit including a first scan chain configured to operate based on a first clock signal and a second scan chain configured to operate based on a second clock signal in a built-in self-test; a pattern generator configured to generate a test pattern and transmit the test pattern to the first and second scan chains; a compression circuit configured to compress first data received from the first and second scan chains; a clock select circuit configured to select one of the first and second clock signals and transmit the one of the first and second clock signals to the corresponding one of the first and second scan chains in the test; and a test control circuit configured to control the test and detect a fault in the logic circuit based on a result of the test.