The present disclosure provides a technology for precisely controlling an LED driving current using fine current trimming data stored in a memory when driving an LED.

A reference buffer has many legs each with an upper transistor, a lower transistor, and a resistor or current source as a tail device in series. The source or emitter of the upper (lower) transistor generates an upper (lower) reference voltage. This source follower transistor configuration has a low output impedance and high current. The gate or base of the upper (lower) transistors are driven by a first (second) control node. A control leg has an upper transistor, a lower transistor, and a tail device in series. The source and gate, or emitter and base, are connected together for the upper and lower transistors and generate the upper and lower control nodes. Alternately, the gate or base of the upper (lower) transistor is driven by an op amp receiving an upper (lower) bandgap voltage and the upper (lower) control node as negative feedback.

A system and method for retaining dynamic random access memory (DRAM) data when reprogramming reconfigurable devices with DRAM memory controllers such as field programmable gate arrays (FPGAs). The DRAM memory controller is utilized in concert with a data maintenance block collocated with the DRAM memory and coupled to an I2C interface of the reconfigurable device, wherein the FPGA drives the majority of the DRAM input/output (I/O) and the data maintenance block drives the self-refresh command inputs. Even though the FPGA reconfigures and the majority of the DRAM inputs are tri-stated, the data maintenance block provides stable input levels on the self-refresh command inputs.

A reference voltage generating circuit includes: an operational amplifier including a first input terminal connected to a first node and a second input terminal connected to a second node; a first transistor connected between a ground terminal and the first node, wherein a first current flows in the first transistor; a second transistor connected to the ground terminal; and a first variable resistor connected between the second transistor and the second node, wherein the first variable resistor has a first resistance value for adjusting the first current, based on a change in a current characteristic of the first transistor caused by a variation in a process of forming the first transistor. The reference voltage generating circuit provides a reference voltage, based on a voltage of the first node and a voltage across the first variable resistor.

A reference voltage generating circuit includes: an operational amplifier including a first input terminal connected to a first node and a second input terminal connected to a second node; a first transistor connected between a ground terminal and the first node, wherein a first current flows in the first transistor; a second transistor connected to the ground terminal; and a first variable resistor connected between the second transistor and the second node, wherein the first variable resistor has a first resistance value for adjusting the first current, based on a change in a current characteristic of the first transistor caused by a variation in a process of forming the first transistor. The reference voltage generating circuit provides a reference voltage, based on a voltage of the first node and a voltage across the first variable resistor.

A reference buffer has many legs each with an upper transistor, a lower transistor, and a resistor or current source as a tail device in series. The source or emitter of the upper (lower) transistor generates an upper (lower) reference voltage. This source follower transistor configuration has a low output impedance and high current. The gate or base of the upper (lower) transistors are driven by a first (second) control node. A control leg has an upper transistor, a lower transistor, and a tail device in series. The source and gate, or emitter and base, are connected together for the upper and lower transistors and generate the upper and lower control nodes. Alternately, the gate or base of the upper (lower) transistor is driven by an op amp receiving an upper (lower) bandgap voltage and the upper (lower) control node as negative feedback.

The invention relates to a method for distributing the total power of an energy conversion device between at least two converters in said energy conversion device, the sum of the conversion powers of the converters being the total power of the conversion device, the energy conversion device converting energy between a first electrical entity and a second electrical entity, characterised in that: said at least two converters correspond to at least two portions of a ring (29), the portions being proportional to a predetermined power value of the respective converters (1) thereof, the combination of the at least two portions forming the whole ring; and in that the total power of the conversion device corresponds to an arc of the ring between the positions of a first slider and a second slider that are movable around the ring, and the distribution of power between the converters is determined by the positions of the first slider and the second slider that are movable around the ring.

The invention relates to a method for distributing the total power of an energy conversion device between at least two converters in said energy conversion device, the sum of the conversion powers of the converters being the total power of the conversion device, the energy conversion device converting energy between a first electrical entity and a second electrical entity, characterised in that: said at least two converters correspond to at least two portions of a ring (29), the portions being proportional to a predetermined power value of the respective converters (1) thereof, the combination of the at least two portions forming the whole ring; and in that the total power of the conversion device corresponds to an arc of the ring between the positions of a first slider and a second slider that are movable around the ring, and the distribution of power between the converters is determined by the positions of the first slider and the second slider that are movable around the ring.

A bandgap reference generation circuit in an integrated circuit (IC) and method for generating a bandgap reference voltage are disclosed. The bandgap reference generation circuit includes a first proportional to absolute temperature (PTAT) current generation section for generating a PTAT current component, a current circuit configured to generate a trimmed PTAT current component substantially invariant of sheet resistance of at least one resistor in the current circuit, and a complementary to absolute temperature (CTAT) current generation section including a diode on which the trimmed PTAT current component is fed to generate a CTAT current component. A combination of the PTAT and CTAT current components generate the bandgap reference voltage.

A wireless power transmitter includes: a current adjuster configured to convert an input power into a transmission current, which is periodically varied according to a transmission frequency; and a power transmitter configured to receive the transmission current and wirelessly transmit power according to the transmission frequency.