The present disclosure provides a single-loop memory device, a double-loop memory device, and a ZQ calibration method. The single-loop memory device includes: a master chip and a plurality of slave chips each provided with a first transmission terminal and a second transmission terminal, where the second transmission terminal of the master chip is connected to the first transmission terminal of the slave chip of a first stage, and the second transmission terminal of the slave chip of each stage is connected to the first transmission terminal of the slave chip of a next stage; and the master chip is provided with a first signal receiver, and the slave chip is provided with a second signal receiver.